Lines Matching +full:s +full:- +full:mode
7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
96 * @mode: The operating mode for the SPI interface. The interface
105 int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, in cvmx_spi_start_interface() argument
108 int res = -1; in cvmx_spi_start_interface()
114 INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); in cvmx_spi_start_interface()
117 INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode, in cvmx_spi_start_interface()
121 INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); in cvmx_spi_start_interface()
124 INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); in cvmx_spi_start_interface()
127 INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, in cvmx_spi_start_interface()
131 INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); in cvmx_spi_start_interface()
142 * @mode: The operating mode for the SPI interface. The interface
150 int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) in cvmx_spi_restart_interface() argument
152 int res = -1; in cvmx_spi_restart_interface()
157 cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]); in cvmx_spi_restart_interface()
160 INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); in cvmx_spi_restart_interface()
166 INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); in cvmx_spi_restart_interface()
169 INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); in cvmx_spi_restart_interface()
172 INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, in cvmx_spi_restart_interface()
176 INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); in cvmx_spi_restart_interface()
187 * @mode: The operating mode for the SPI interface. The interface
192 * Returns Zero on success, non-zero error code on failure (will cause
195 int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) in cvmx_spi_reset_cb() argument
204 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_reset_cb()
216 spxx_clk_ctl.s.runbist = 1; in cvmx_spi_reset_cb()
220 if (spxx_bist_stat.s.stat0) in cvmx_spi_reset_cb()
224 if (spxx_bist_stat.s.stat1) in cvmx_spi_reset_cb()
227 if (spxx_bist_stat.s.stat2) in cvmx_spi_reset_cb()
237 srxx_spi4_calx.s.oddpar = 1; in cvmx_spi_reset_cb()
242 stxx_spi4_calx.s.oddpar = 1; in cvmx_spi_reset_cb()
257 spxx_clk_ctl.s.seetrn = 0; in cvmx_spi_reset_cb()
258 spxx_clk_ctl.s.clkdly = 0x10; in cvmx_spi_reset_cb()
259 spxx_clk_ctl.s.runbist = 0; in cvmx_spi_reset_cb()
260 spxx_clk_ctl.s.statdrv = 0; in cvmx_spi_reset_cb()
262 spxx_clk_ctl.s.statrcv = 1; in cvmx_spi_reset_cb()
263 spxx_clk_ctl.s.sndtrn = 0; in cvmx_spi_reset_cb()
264 spxx_clk_ctl.s.drptrn = 0; in cvmx_spi_reset_cb()
265 spxx_clk_ctl.s.rcvtrn = 0; in cvmx_spi_reset_cb()
266 spxx_clk_ctl.s.srxdlck = 0; in cvmx_spi_reset_cb()
271 spxx_clk_ctl.s.srxdlck = 1; in cvmx_spi_reset_cb()
278 spxx_trn4_ctl.s.trntest = 0; in cvmx_spi_reset_cb()
279 spxx_trn4_ctl.s.jitter = 1; in cvmx_spi_reset_cb()
280 spxx_trn4_ctl.s.clr_boot = 1; in cvmx_spi_reset_cb()
281 spxx_trn4_ctl.s.set_boot = 0; in cvmx_spi_reset_cb()
283 spxx_trn4_ctl.s.maxdist = 3; in cvmx_spi_reset_cb()
285 spxx_trn4_ctl.s.maxdist = 8; in cvmx_spi_reset_cb()
286 spxx_trn4_ctl.s.macro_en = 1; in cvmx_spi_reset_cb()
287 spxx_trn4_ctl.s.mux_en = 1; in cvmx_spi_reset_cb()
302 * @mode: The operating mode for the SPI interface. The interface
308 * Returns Zero on success, non-zero error code on failure (will cause
311 int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, in cvmx_spi_calendar_setup_cb() argument
316 if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { in cvmx_spi_calendar_setup_cb()
322 srxx_com_ctl.s.prts = num_ports - 1; in cvmx_spi_calendar_setup_cb()
323 srxx_com_ctl.s.st_en = 0; in cvmx_spi_calendar_setup_cb()
324 srxx_com_ctl.s.inf_en = 0; in cvmx_spi_calendar_setup_cb()
333 srxx_spi4_calx.s.prt0 = port++; in cvmx_spi_calendar_setup_cb()
334 srxx_spi4_calx.s.prt1 = port++; in cvmx_spi_calendar_setup_cb()
335 srxx_spi4_calx.s.prt2 = port++; in cvmx_spi_calendar_setup_cb()
336 srxx_spi4_calx.s.prt3 = port++; in cvmx_spi_calendar_setup_cb()
337 srxx_spi4_calx.s.oddpar = in cvmx_spi_calendar_setup_cb()
344 srxx_spi4_stat.s.len = num_ports; in cvmx_spi_calendar_setup_cb()
345 srxx_spi4_stat.s.m = 1; in cvmx_spi_calendar_setup_cb()
350 if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { in cvmx_spi_calendar_setup_cb()
360 stxx_arb_ctl.s.igntpa = 0; in cvmx_spi_calendar_setup_cb()
361 stxx_arb_ctl.s.mintrn = 0; in cvmx_spi_calendar_setup_cb()
365 gmxx_tx_spi_max.s.max1 = 8; in cvmx_spi_calendar_setup_cb()
366 gmxx_tx_spi_max.s.max2 = 4; in cvmx_spi_calendar_setup_cb()
367 gmxx_tx_spi_max.s.slice = 0; in cvmx_spi_calendar_setup_cb()
372 gmxx_tx_spi_thresh.s.thresh = 4; in cvmx_spi_calendar_setup_cb()
377 gmxx_tx_spi_ctl.s.tpa_clr = 0; in cvmx_spi_calendar_setup_cb()
378 gmxx_tx_spi_ctl.s.cont_pkt = 0; in cvmx_spi_calendar_setup_cb()
385 stxx_spi4_dat.s.alpha = 32; in cvmx_spi_calendar_setup_cb()
386 stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */ in cvmx_spi_calendar_setup_cb()
396 stxx_spi4_calx.s.prt0 = port++; in cvmx_spi_calendar_setup_cb()
397 stxx_spi4_calx.s.prt1 = port++; in cvmx_spi_calendar_setup_cb()
398 stxx_spi4_calx.s.prt2 = port++; in cvmx_spi_calendar_setup_cb()
399 stxx_spi4_calx.s.prt3 = port++; in cvmx_spi_calendar_setup_cb()
400 stxx_spi4_calx.s.oddpar = in cvmx_spi_calendar_setup_cb()
407 stxx_spi4_stat.s.len = num_ports; in cvmx_spi_calendar_setup_cb()
408 stxx_spi4_stat.s.m = 1; in cvmx_spi_calendar_setup_cb()
421 * @mode: The operating mode for the SPI interface. The interface
427 * Returns Zero on success, non-zero error code on failure (will cause
430 int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) in cvmx_spi_clock_detect_cb() argument
435 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_clock_detect_cb()
438 * Regardless of operating mode, both Tx and Rx clocks must be in cvmx_spi_clock_detect_cb()
450 if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { in cvmx_spi_clock_detect_cb()
455 clock_transitions--; in cvmx_spi_clock_detect_cb()
457 stat.s.s4clk0 = 0; in cvmx_spi_clock_detect_cb()
458 stat.s.s4clk1 = 0; in cvmx_spi_clock_detect_cb()
462 return -1; in cvmx_spi_clock_detect_cb()
464 } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); in cvmx_spi_clock_detect_cb()
475 if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) { in cvmx_spi_clock_detect_cb()
480 clock_transitions--; in cvmx_spi_clock_detect_cb()
482 stat.s.d4clk0 = 0; in cvmx_spi_clock_detect_cb()
483 stat.s.d4clk1 = 0; in cvmx_spi_clock_detect_cb()
487 return -1; in cvmx_spi_clock_detect_cb()
489 } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0); in cvmx_spi_clock_detect_cb()
499 * @mode: The operating mode for the SPI interface. The interface
505 * Returns Zero on success, non-zero error code on failure (will cause
508 int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) in cvmx_spi_training_cb() argument
512 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_training_cb()
516 /* SRX0 & STX0 Inf0 Links are configured - begin training */ in cvmx_spi_training_cb()
519 spxx_clk_ctl.s.seetrn = 0; in cvmx_spi_training_cb()
520 spxx_clk_ctl.s.clkdly = 0x10; in cvmx_spi_training_cb()
521 spxx_clk_ctl.s.runbist = 0; in cvmx_spi_training_cb()
522 spxx_clk_ctl.s.statdrv = 0; in cvmx_spi_training_cb()
524 spxx_clk_ctl.s.statrcv = 1; in cvmx_spi_training_cb()
525 spxx_clk_ctl.s.sndtrn = 1; in cvmx_spi_training_cb()
526 spxx_clk_ctl.s.drptrn = 1; in cvmx_spi_training_cb()
527 spxx_clk_ctl.s.rcvtrn = 1; in cvmx_spi_training_cb()
528 spxx_clk_ctl.s.srxdlck = 1; in cvmx_spi_training_cb()
534 spxx_trn4_ctl.s.clr_boot = 1; in cvmx_spi_training_cb()
549 if (stat.s.srxtrn && rx_training_needed) { in cvmx_spi_training_cb()
550 rx_training_needed--; in cvmx_spi_training_cb()
552 stat.s.srxtrn = 0; in cvmx_spi_training_cb()
556 return -1; in cvmx_spi_training_cb()
558 } while (stat.s.srxtrn == 0); in cvmx_spi_training_cb()
568 * @mode: The operating mode for the SPI interface. The interface
574 * Returns Zero on success, non-zero error code on failure (will cause
577 int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) in cvmx_spi_calendar_sync_cb() argument
579 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_calendar_sync_cb()
580 if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { in cvmx_spi_calendar_sync_cb()
587 srxx_com_ctl.s.inf_en = 1; in cvmx_spi_calendar_sync_cb()
588 srxx_com_ctl.s.st_en = 1; in cvmx_spi_calendar_sync_cb()
592 if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { in cvmx_spi_calendar_sync_cb()
600 stxx_com_ctl.s.st_en = 1; in cvmx_spi_calendar_sync_cb()
607 /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */ in cvmx_spi_calendar_sync_cb()
612 return -1; in cvmx_spi_calendar_sync_cb()
614 } while (stat.s.stxcal == 0); in cvmx_spi_calendar_sync_cb()
625 * @mode: The operating mode for the SPI interface. The interface
630 * Returns Zero on success, non-zero error code on failure (will cause
633 int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) in cvmx_spi_interface_up_cb() argument
639 if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { in cvmx_spi_interface_up_cb()
642 srxx_com_ctl.s.inf_en = 1; in cvmx_spi_interface_up_cb()
647 if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { in cvmx_spi_interface_up_cb()
650 stxx_com_ctl.s.inf_en = 1; in cvmx_spi_interface_up_cb()
656 gmxx_rxx_frm_min.s.len = 64; in cvmx_spi_interface_up_cb()
660 gmxx_rxx_frm_max.s.len = 64 * 1024 - 4; in cvmx_spi_interface_up_cb()
664 gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4; in cvmx_spi_interface_up_cb()