Lines Matching refs:sysc
155 sysc: syscon@0 { label
156 compatible = "mediatek,mt7621-sysc", "syscon";
172 mediatek,sysctl = <&sysc>;
197 clocks = <&sysc MT7621_CLK_I2C>;
203 resets = <&sysc MT7621_RST_I2C>;
221 clocks = <&sysc MT7621_CLK_UART1>;
239 clocks = <&sysc MT7621_CLK_UART2>;
259 clocks = <&sysc MT7621_CLK_UART3>;
280 clocks = <&sysc MT7621_CLK_SPI>;
286 resets = <&sysc MT7621_RST_SPI>;
301 clocks = <&sysc MT7621_CLK_SHXC>,
302 <&sysc MT7621_CLK_50M>;
331 clocks = <&sysc MT7621_CLK_XTAL>;
349 clocks = <&sysc MT7621_CLK_CPU>;
372 clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
381 resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
383 mediatek,ethsys = <&sysc>;
398 resets = <&sysc MT7621_RST_MCM>;
528 clocks = <&sysc MT7621_CLK_PCIE0>;
538 resets = <&sysc MT7621_RST_PCIE0>;
549 clocks = <&sysc MT7621_CLK_PCIE1>;
559 resets = <&sysc MT7621_RST_PCIE1>;
570 clocks = <&sysc MT7621_CLK_PCIE2>;
580 resets = <&sysc MT7621_RST_PCIE2>;
590 clocks = <&sysc MT7621_CLK_XTAL>;
599 clocks = <&sysc MT7621_CLK_XTAL>;