dts/ralink/mt7621.dtsi

15 		#size-cells = <0>;
17 		cpu@0 {
19 			reg = <0>;
33 		#address-cells = <0>;
149 		reg = <0x1e000000 0x100000>;
150 		ranges = <0x0 0x1e000000 0x0fffff>;
155 		sysc: syscon@0 {
157 			reg = <0x0 0x100>;
171 			reg = <0x100 0x100>;
177 			reg = <0x600 0x100>;
183 			gpio-ranges = <&pinctrl 0 0 95>;
192 			reg = <0x900 0x100>;
195 			#size-cells = <0>;
201 			pinctrl-0 = <&i2c_pins>;
211 			reg = <0x5000 0x1000>;
216 			reg = <0xc00 0x100>;
229 			pinctrl-0 = <&uart1_pins>;
234 			reg = <0xd00 0x100>;
247 			pinctrl-0 = <&uart2_pins>;
254 			reg = <0xe00 0x100>;
267 			pinctrl-0 = <&uart3_pins>;
274 			reg = <0xb00 0x100>;
277 			#size-cells = <0>;
283 			pinctrl-0 = <&spi_pins>;
294 		reg = <0x1e130000 0x4000>;
313 		pinctrl-0 = <&sdhci_pins>;
324 		reg = <0x1e1c0000 0x1000
325 		       0x1e1d0700 0x0100>;
329 		#size-cells = <0>;
340 		reg = <0x1fbc0000 0x2000>;
356 		reg = <0x1fbf0000 0x8000>;
361 		reg = <0x1fbf8000 0x8000>;
366 		reg = <0x1e100000 0x10000>;
369 		#size-cells = <0>;
378 		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
387 			#size-cells = <0>;
391 				reg = <0x1f>;
404 					#size-cells = <0>;
406 					port@0 {
407 						reg = <0>;
465 		gmac0: mac@0 {
467 			reg = <0>;
495 		reg = <0x1e140000 0x100>, /* host-pci bridge registers */
496 		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */
497 		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */
498 		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */
499 		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
500 			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
508 		interrupt-map-mask = <0xf800 0 0 0>;
509 		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED  4 IRQ_TYPE_LEVEL_HIGH>,
510 				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
511 				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
514 		pinctrl-0 = <&pcie_pins>;
520 		pcie@0,0 {
521 			reg = <0x0000 0 0 0 0>;
532 			interrupt-map-mask = <0 0 0 0>;
533 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
541 		pcie@1,0 {
542 			reg = <0x0800 0 0 0 0>;
553 			interrupt-map-mask = <0 0 0 0>;
554 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
562 		pcie@2,0 {
563 			reg = <0x1000 0 0 0 0>;
574 			interrupt-map-mask = <0 0 0 0>;
575 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
578 			phys = <&pcie2_phy 0>;
586 		reg = <0x1e149000 0x0700>;
595 		reg = <0x1e14a000 0x0700>;