dts/mscc/ocelot_pcb120.dts

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
9 #include "ocelot.dtsi"
12 	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 		stdout-path = "serial0:115200n8";
25 	phy_int_pins: phy-int-pins {
30 	phy_load_save_pins: phy-load-save-pins {
42 	pinctrl-names = "default";
43 	pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
45 	phy7: ethernet-phy@0 {
48 		interrupt-parent = <&gpio>;
49 		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
51 	phy6: ethernet-phy@1 {
54 		interrupt-parent = <&gpio>;
55 		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
57 	phy5: ethernet-phy@2 {
60 		interrupt-parent = <&gpio>;
61 		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
63 	phy4: ethernet-phy@3 {
66 		interrupt-parent = <&gpio>;
67 		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
73 	phy-handle = <&phy0>;
74 	phy-mode = "internal";
79 	phy-handle = <&phy1>;
80 	phy-mode = "internal";
85 	phy-handle = <&phy2>;
86 	phy-mode = "internal";
91 	phy-handle = <&phy3>;
92 	phy-mode = "internal";
97 	phy-handle = <&phy7>;
98 	phy-mode = "sgmii";
99 	phys = <&serdes 4 SERDES1G(2)>;
104 	phy-handle = <&phy4>;
105 	phy-mode = "sgmii";
106 	phys = <&serdes 5 SERDES1G(5)>;
111 	phy-handle = <&phy6>;
112 	phy-mode = "sgmii";
113 	phys = <&serdes 6 SERDES1G(3)>;
118 	phy-handle = <&phy5>;
119 	phy-mode = "sgmii";
120 	phys = <&serdes 9 SERDES1G(4)>;