Lines Matching +full:0 +full:x1f00000

16 		reg = <0x0 0x2000000>;
26 			reg = <0x1f00000 0x100000>;
42 		pwms = <&pwm 3 40000 0>;
44 		brightness-levels = <0 16 32 48 64 80 112 144 192 255>;
48 		pinctrl-0 = <&pins_pwm3>;
53 	keys@0 {
56 		key-0 {
113 		key@0 {
169 		#phy-cells = <0>;
234 	pinctrl-0 = <&pins_mmc1>;
250 		reg = <1 0 0x4000000>;
253 		#size-cells = <0>;
264 		pinctrl-0 = <&pins_nemc>;
282 				partition@0 {
284 					reg = <0x0 0x20000>;
289 					reg = <0x20000 0x0>;
308 	assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
316 	pinctrl-0 = <&pins_lcd>;
320 	port@0 {
321 		reg = <0>;