dts/cavium-octeon/octeon_68xx.dts

1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7  * use.	 Because of this, it contains a super-set of the available
11 	compatible = "cavium,octeon-6880";
12 	#address-cells = <2>;
13 	#size-cells = <2>;
14 	interrupt-parent = <&ciu2>;
17 		compatible = "simple-bus";
18 		#address-cells = <2>;
19 		#size-cells = <2>;
22 		ciu2: interrupt-controller@1070100000000 {
23 			compatible = "cavium,octeon-6880-ciu2";
24 			interrupt-controller;
29 			#address-cells = <0>;
30 			#interrupt-cells = <2>;
34 		gpio: gpio-controller@1070000000800 {
35 			#gpio-cells = <2>;
36 			compatible = "cavium,octeon-3860-gpio";
38 			gpio-controller;
41 			 * 2) Triggering (1 - edge rising
42 			 *		  2 - edge falling
43 			 *		  4 - level active high
44 			 *		  8 - level active low)
46 			interrupt-controller;
47 			#interrupt-cells = <2>;
49 			interrupts = <7 0>,  <7 1>,  <7 2>,  <7 3>,
56 			compatible = "cavium,octeon-3860-mdio";
57 			#address-cells = <1>;
58 			#size-cells = <0>;
61 			phy0: ethernet-phy@6 {
63 				marvell,reg-init =
67 					<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
68 					/* irq, blink-activity, blink-link */
69 					<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
73 			phy1: ethernet-phy@1 {
74 				cavium,qlm-trim = "4,sgmii";
77 				marvell,reg-init = <3 0x10 0 0x5777>,
78 					<3 0x11 0 0x00aa>,
79 					<3 0x12 0 0x4105>,
80 					<3 0x13 0 0x0a60>;
82 			phy2: ethernet-phy@2 {
83 				cavium,qlm-trim = "4,sgmii";
86 				marvell,reg-init = <3 0x10 0 0x5777>,
87 					<3 0x11 0 0x00aa>,
88 					<3 0x12 0 0x4105>,
89 					<3 0x13 0 0x0a60>;
91 			phy3: ethernet-phy@3 {
92 				cavium,qlm-trim = "4,sgmii";
93 				reg = <3>;
95 				marvell,reg-init = <3 0x10 0 0x5777>,
96 					<3 0x11 0 0x00aa>,
97 					<3 0x12 0 0x4105>,
98 					<3 0x13 0 0x0a60>;
100 			phy4: ethernet-phy@4 {
101 				cavium,qlm-trim = "4,sgmii";
104 				marvell,reg-init = <3 0x10 0 0x5777>,
105 					<3 0x11 0 0x00aa>,
106 					<3 0x12 0 0x4105>,
107 					<3 0x13 0 0x0a60>;
112 			compatible = "cavium,octeon-3860-mdio";
113 			#address-cells = <1>;
114 			#size-cells = <0>;
117 			phy41: ethernet-phy@1 {
118 				cavium,qlm-trim = "0,sgmii";
121 				marvell,reg-init = <3 0x10 0 0x5777>,
122 					<3 0x11 0 0x00aa>,
123 					<3 0x12 0 0x4105>,
124 					<3 0x13 0 0x0a60>;
126 			phy42: ethernet-phy@2 {
127 				cavium,qlm-trim = "0,sgmii";
130 				marvell,reg-init = <3 0x10 0 0x5777>,
131 					<3 0x11 0 0x00aa>,
132 					<3 0x12 0 0x4105>,
133 					<3 0x13 0 0x0a60>;
135 			phy43: ethernet-phy@3 {
136 				cavium,qlm-trim = "0,sgmii";
137 				reg = <3>;
139 				marvell,reg-init = <3 0x10 0 0x5777>,
140 					<3 0x11 0 0x00aa>,
141 					<3 0x12 0 0x4105>,
142 					<3 0x13 0 0x0a60>;
144 			phy44: ethernet-phy@4 {
145 				cavium,qlm-trim = "0,sgmii";
148 				marvell,reg-init = <3 0x10 0 0x5777>,
149 					<3 0x11 0 0x00aa>,
150 					<3 0x12 0 0x4105>,
151 					<3 0x13 0 0x0a60>;
156 			compatible = "cavium,octeon-3860-mdio";
157 			#address-cells = <1>;
158 			#size-cells = <0>;
161 			phy21: ethernet-phy@1 {
162 				cavium,qlm-trim = "2,sgmii";
165 				marvell,reg-init = <3 0x10 0 0x5777>,
166 					<3 0x11 0 0x00aa>,
167 					<3 0x12 0 0x4105>,
168 					<3 0x13 0 0x0a60>;
170 			phy22: ethernet-phy@2 {
171 				cavium,qlm-trim = "2,sgmii";
174 				marvell,reg-init = <3 0x10 0 0x5777>,
175 					<3 0x11 0 0x00aa>,
176 					<3 0x12 0 0x4105>,
177 					<3 0x13 0 0x0a60>;
179 			phy23: ethernet-phy@3 {
180 				cavium,qlm-trim = "2,sgmii";
181 				reg = <3>;
183 				marvell,reg-init = <3 0x10 0 0x5777>,
184 					<3 0x11 0 0x00aa>,
185 					<3 0x12 0 0x4105>,
186 					<3 0x13 0 0x0a60>;
188 			phy24: ethernet-phy@4 {
189 				cavium,qlm-trim = "2,sgmii";
192 				marvell,reg-init = <3 0x10 0 0x5777>,
193 					<3 0x11 0 0x00aa>,
194 					<3 0x12 0 0x4105>,
195 					<3 0x13 0 0x0a60>;
200 			compatible = "cavium,octeon-3860-mdio";
201 			#address-cells = <1>;
202 			#size-cells = <0>;
205 			phy11: ethernet-phy@1 {
206 				cavium,qlm-trim = "3,sgmii";
209 				marvell,reg-init = <3 0x10 0 0x5777>,
210 					<3 0x11 0 0x00aa>,
211 					<3 0x12 0 0x4105>,
212 					<3 0x13 0 0x0a60>;
214 			phy12: ethernet-phy@2 {
215 				cavium,qlm-trim = "3,sgmii";
218 				marvell,reg-init = <3 0x10 0 0x5777>,
219 					<3 0x11 0 0x00aa>,
220 					<3 0x12 0 0x4105>,
221 					<3 0x13 0 0x0a60>;
223 			phy13: ethernet-phy@3 {
224 				cavium,qlm-trim = "3,sgmii";
225 				reg = <3>;
227 				marvell,reg-init = <3 0x10 0 0x5777>,
228 					<3 0x11 0 0x00aa>,
229 					<3 0x12 0 0x4105>,
230 					<3 0x13 0 0x0a60>;
232 			phy14: ethernet-phy@4 {
233 				cavium,qlm-trim = "3,sgmii";
236 				marvell,reg-init = <3 0x10 0 0x5777>,
237 					<3 0x11 0 0x00aa>,
238 					<3 0x12 0 0x4105>,
239 					<3 0x13 0 0x0a60>;
244 			compatible = "cavium,octeon-5750-mix";
249 			cell-index = <0>;
251 			local-mac-address = [ 00 00 00 00 00 00 ];
252 			phy-handle = <&phy0>;
256 			compatible = "cavium,octeon-3860-pip";
257 			#address-cells = <1>;
258 			#size-cells = <0>;
262 				compatible = "cavium,octeon-3860-pip-interface";
263 				#address-cells = <1>;
264 				#size-cells = <0>;
268 					compatible = "cavium,octeon-3860-pip-port";
269 					reg = <0x0>; /* Port */
270 					local-mac-address = [ 00 00 00 00 00 00 ];
271 					phy-handle = <&phy1>;
274 					compatible = "cavium,octeon-3860-pip-port";
275 					reg = <0x1>; /* Port */
276 					local-mac-address = [ 00 00 00 00 00 00 ];
277 					phy-handle = <&phy2>;
280 					compatible = "cavium,octeon-3860-pip-port";
281 					reg = <0x2>; /* Port */
282 					local-mac-address = [ 00 00 00 00 00 00 ];
283 					phy-handle = <&phy3>;
285 				ethernet@3 {
286 					compatible = "cavium,octeon-3860-pip-port";
287 					reg = <0x3>; /* Port */
288 					local-mac-address = [ 00 00 00 00 00 00 ];
289 					phy-handle = <&phy4>;
293 			interface@3 {
294 				compatible = "cavium,octeon-3860-pip-interface";
295 				#address-cells = <1>;
296 				#size-cells = <0>;
300 					compatible = "cavium,octeon-3860-pip-port";
301 					reg = <0x0>; /* Port */
302 					local-mac-address = [ 00 00 00 00 00 00 ];
303 					phy-handle = <&phy11>;
306 					compatible = "cavium,octeon-3860-pip-port";
307 					reg = <0x1>; /* Port */
308 					local-mac-address = [ 00 00 00 00 00 00 ];
309 					phy-handle = <&phy12>;
312 					compatible = "cavium,octeon-3860-pip-port";
313 					reg = <0x2>; /* Port */
314 					local-mac-address = [ 00 00 00 00 00 00 ];
315 					phy-handle = <&phy13>;
317 				ethernet@3 {
318 					compatible = "cavium,octeon-3860-pip-port";
319 					reg = <0x3>; /* Port */
320 					local-mac-address = [ 00 00 00 00 00 00 ];
321 					phy-handle = <&phy14>;
326 				compatible = "cavium,octeon-3860-pip-interface";
327 				#address-cells = <1>;
328 				#size-cells = <0>;
332 					compatible = "cavium,octeon-3860-pip-port";
333 					reg = <0x0>; /* Port */
334 					local-mac-address = [ 00 00 00 00 00 00 ];
335 					phy-handle = <&phy21>;
338 					compatible = "cavium,octeon-3860-pip-port";
339 					reg = <0x1>; /* Port */
340 					local-mac-address = [ 00 00 00 00 00 00 ];
341 					phy-handle = <&phy22>;
344 					compatible = "cavium,octeon-3860-pip-port";
345 					reg = <0x2>; /* Port */
346 					local-mac-address = [ 00 00 00 00 00 00 ];
347 					phy-handle = <&phy23>;
349 				ethernet@3 {
350 					compatible = "cavium,octeon-3860-pip-port";
351 					reg = <0x3>; /* Port */
352 					local-mac-address = [ 00 00 00 00 00 00 ];
353 					phy-handle = <&phy24>;
358 				compatible = "cavium,octeon-3860-pip-interface";
359 				#address-cells = <1>;
360 				#size-cells = <0>;
364 					compatible = "cavium,octeon-3860-pip-port";
365 					reg = <0x0>; /* Port */
366 					local-mac-address = [ 00 00 00 00 00 00 ];
371 				compatible = "cavium,octeon-3860-pip-interface";
372 				#address-cells = <1>;
373 				#size-cells = <0>;
377 					compatible = "cavium,octeon-3860-pip-port";
378 					reg = <0x0>; /* Port */
379 					local-mac-address = [ 00 00 00 00 00 00 ];
380 					phy-handle = <&phy41>;
383 					compatible = "cavium,octeon-3860-pip-port";
384 					reg = <0x1>; /* Port */
385 					local-mac-address = [ 00 00 00 00 00 00 ];
386 					phy-handle = <&phy42>;
389 					compatible = "cavium,octeon-3860-pip-port";
390 					reg = <0x2>; /* Port */
391 					local-mac-address = [ 00 00 00 00 00 00 ];
392 					phy-handle = <&phy43>;
394 				ethernet@3 {
395 					compatible = "cavium,octeon-3860-pip-port";
396 					reg = <0x3>; /* Port */
397 					local-mac-address = [ 00 00 00 00 00 00 ];
398 					phy-handle = <&phy44>;
404 			#address-cells = <1>;
405 			#size-cells = <0>;
406 			compatible = "cavium,octeon-3860-twsi";
408 			interrupts = <3 32>;
409 			clock-frequency = <100000>;
422 			#address-cells = <1>;
423 			#size-cells = <0>;
424 			compatible = "cavium,octeon-3860-twsi";
426 			interrupts = <3 33>;
427 			clock-frequency = <100000>;
431 			compatible = "cavium,octeon-3860-uart","ns16550";
433 			clock-frequency = <0>;
434 			current-speed = <115200>;
435 			reg-shift = <3>;
436 			interrupts = <3 36>;
440 			compatible = "cavium,octeon-3860-uart","ns16550";
442 			clock-frequency = <0>;
443 			current-speed = <115200>;
444 			reg-shift = <3>;
445 			interrupts = <3 37>;
449 			compatible = "cavium,octeon-3860-bootbus";
452 			#address-cells = <2>;
454 			#size-cells = <1>;
458 				 <3 0  0x10000 0x50000000  0>,
464 			cavium,cs-config@0 {
465 				compatible = "cavium,octeon-3860-bootbus-config";
466 				cavium,cs-index = <0>;
467 				cavium,t-adr  = <10>;
468 				cavium,t-ce   = <50>;
469 				cavium,t-oe   = <50>;
470 				cavium,t-we   = <35>;
471 				cavium,t-rd-hld = <25>;
472 				cavium,t-wr-hld = <35>;
473 				cavium,t-pause	= <0>;
474 				cavium,t-wait	= <300>;
475 				cavium,t-page	= <25>;
476 				cavium,t-rd-dly = <0>;
479 				cavium,bus-width = <8>;
481 			cavium,cs-config@4 {
482 				compatible = "cavium,octeon-3860-bootbus-config";
483 				cavium,cs-index = <4>;
484 				cavium,t-adr  = <320>;
485 				cavium,t-ce   = <320>;
486 				cavium,t-oe   = <320>;
487 				cavium,t-we   = <320>;
488 				cavium,t-rd-hld = <320>;
489 				cavium,t-wr-hld = <320>;
490 				cavium,t-pause	= <320>;
491 				cavium,t-wait	= <320>;
492 				cavium,t-page	= <320>;
493 				cavium,t-rd-dly = <0>;
496 				cavium,bus-width = <8>;
498 			cavium,cs-config@5 {
499 				compatible = "cavium,octeon-3860-bootbus-config";
500 				cavium,cs-index = <5>;
501 				cavium,t-adr  = <0>;
502 				cavium,t-ce   = <300>;
503 				cavium,t-oe   = <125>;
504 				cavium,t-we   = <150>;
505 				cavium,t-rd-hld = <100>;
506 				cavium,t-wr-hld = <300>;
507 				cavium,t-pause	= <0>;
508 				cavium,t-wait	= <300>;
509 				cavium,t-page	= <310>;
510 				cavium,t-rd-dly = <0>;
513 				cavium,bus-width = <16>;
515 			cavium,cs-config@6 {
516 				compatible = "cavium,octeon-3860-bootbus-config";
517 				cavium,cs-index = <6>;
518 				cavium,t-adr  = <0>;
519 				cavium,t-ce   = <30>;
520 				cavium,t-oe   = <125>;
521 				cavium,t-we   = <150>;
522 				cavium,t-rd-hld = <100>;
523 				cavium,t-wr-hld = <30>;
524 				cavium,t-pause	= <0>;
525 				cavium,t-wait	= <30>;
526 				cavium,t-page	= <310>;
527 				cavium,t-rd-dly = <0>;
530 				cavium,wait-mode;
531 				cavium,bus-width = <16>;
535 				compatible = "cfi-flash";
537 				#address-cells = <1>;
538 				#size-cells = <1>;
543 					read-only;
556 					read-only;
560 			led0: led-display@4,0 {
561 				compatible = "avago,hdsp-253x";
565 			compact-flash@5,0 {
566 				compatible = "cavium,ebt3000-compact-flash";
568 				cavium,bus-width = <16>;
569 				cavium,true-ide;
570 				cavium,dma-engine-handle = <&dma0>;
574 		dma0: dma-engine@1180000000100 {
575 			compatible = "cavium,octeon-5750-bootbus-dma";
579 		dma1: dma-engine@1180000000108 {
580 			compatible = "cavium,octeon-5750-bootbus-dma";
586 			compatible = "cavium,octeon-6335-uctl";
589 			#address-cells = <2>;
590 			#size-cells = <2>;
592 			refclk-frequency = <12000000>;
594 			refclk-type = "crystal";
597 				compatible = "cavium,octeon-6335-ehci","usb-ehci";
599 				interrupts = <3 44>;
600 				big-endian-regs;
603 				compatible = "cavium,octeon-6335-ohci","usb-ohci";
605 				interrupts = <3 44>;
606 				big-endian-regs;