Lines Matching +full:0 +full:x68000000
12 soc@0 {
22 * 1) Controller register (0 or 1)
23 * 2) Bit within the register (0..63)
26 reg = <0x10700 0x00000000 0x0 0x7000>;
32 reg = <0x10700 0x00000800 0x0 0x100>;
35 * 1) GPIO pin number (0..15)
44 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
45 <0 20>, <0 21>, <0 22>, <0 23>,
46 <0 24>, <0 25>, <0 26>, <0 27>,
47 <0 28>, <0 29>, <0 30>, <0 31>;
53 #size-cells = <0>;
54 reg = <0x11800 0x00001800 0x0 0x40>;
60 #size-cells = <0>;
61 reg = <0x11800 0xa0000000 0x0 0x2000>;
63 interface@0 {
66 #size-cells = <0>;
67 reg = <0>; /* interface */
69 ethernet@0 {
71 reg = <0x0>; /* Port */
76 reg = <0x1>; /* Port */
81 reg = <0x2>; /* Port */
89 #size-cells = <0>;
96 #size-cells = <0>;
98 reg = <0x11800 0x00001000 0x0 0x200>;
99 interrupts = <0 45>;
105 reg = <0x11800 0x00000800 0x0 0x400>;
106 clock-frequency = <0>;
109 interrupts = <0 34>;
114 reg = <0x11800 0x00000000 0x0 0x200>;
119 ranges = <0 0 0x0 0x1f400000 0xc00000>,
120 <1 0 0x10000 0x30000000 0>,
121 <2 0 0x10000 0x40000000 0>,
122 <3 0 0x10000 0x50000000 0>,
123 <4 0 0x0 0x1d020000 0x10000>,
124 <5 0 0x0 0x1d040000 0x10000>,
125 <6 0 0x0 0x1d050000 0x10000>,
126 <7 0 0x10000 0x90000000 0>;
128 cavium,cs-config@0 {
130 cavium,cs-index = <0>;
137 cavium,t-pause = <0>;
138 cavium,t-wait = <0>;
140 cavium,t-rd-dly = <0>;
142 cavium,pages = <0>;
157 cavium,t-rd-dly = <0>;
159 cavium,pages = <0>;
171 cavium,t-pause = <0>;
174 cavium,t-rd-dly = <0>;
176 cavium,pages = <0>;
188 cavium,t-pause = <0>;
189 cavium,t-wait = <0>;
191 cavium,t-rd-dly = <0>;
193 cavium,pages = <0>;
198 flash0: nor@0,0 {
200 reg = <0 0 0x800000>;
208 reg = <0x11800 0x00000100 0x0 0x8>;
209 interrupts = <0 63>;
214 reg = <0x11800 0x00000108 0x0 0x8>;
215 interrupts = <0 63>;
220 reg = <0x11800 0x68000000 0x0 0x1000>;
227 reg = <0x16f00 0x10000000 0x0 0x80000>;
228 interrupts = <0 56>;