Lines Matching +full:0 +full:x01ffffff

14 #define VSS_GATE	0x00	/* gate wait timers */
15 #define VSS_CLKRST	0x04	/* clock/block control */
16 #define VSS_FTR		0x08	/* footers */
18 #define VSS_ADDR(blk)	(KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
30 	__raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */  in __enable_block()
34 	__raw_writel(0x01, base + VSS_FTR);  in __enable_block()
36 	__raw_writel(0x03, base + VSS_FTR);  in __enable_block()
38 	__raw_writel(0x07, base + VSS_FTR);  in __enable_block()
40 	__raw_writel(0x0f, base + VSS_FTR);  in __enable_block()
43 	__raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */  in __enable_block()
49 	__raw_writel(0x1f, base + VSS_FTR);	/* enable isolation cells */  in __enable_block()
58 	__raw_writel(0x0f, base + VSS_FTR);	/* disable isolation cells */  in __disable_block()
60 	__raw_writel(0, base + VSS_GATE);	/* disable FSM */  in __disable_block()
66 	__raw_writel(0, base + VSS_FTR);	/* disable all footers */  in __disable_block()