Lines Matching +full:loongson +full:- +full:1 +full:b
1 # SPDX-License-Identifier: GPL-2.0
33 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
143 bool "Generic board-agnostic MIPS kernel"
285 Build a generic DT-based kernel image that boots on select
286 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
378 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
379 DECstation porting pages on <http://decstation.unix-ag.org/>.
418 Olivetti M700-10 workstations.
455 bool "Loongson 32-bit family of machines"
458 This enables support for the Loongson-1 family of machines.
460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
465 bool "Loongson-2E/F family of machines"
468 This enables the support of early Loongson-2E/F family of machines.
471 bool "Loongson 64-bit family of machines"
506 This enables the support of Loongson-2/3 family of machines.
508 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
509 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
510 and Loongson-2F which will be removed), developed by the Institute
575 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
830 bool "Sibyte BCM91125C-CRhone"
840 bool "Sibyte BCM91125E-Rhone"
849 bool "Sibyte BCM91250A-SWARM"
862 bool "Sibyte BCM91250C2-LittleSur"
874 bool "Sibyte BCM91250E-Sentosa"
884 bool "Sibyte BCM91480B-BigSur"
933 The SNI RM200/300/400 are MIPS-based machines manufactured by
1012 This requires u-boot on the platform.
1027 source "arch/mips/sgi-ip27/Kconfig"
1030 source "arch/mips/cavium-octeon/Kconfig"
1309 bool "Loongson 64-bit CPU"
1331 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1333 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1335 Loongson-2E/2F is not covered here and will be removed in future.
1338 bool "Loongson 2E"
1342 The Loongson 2E processor implements the MIPS III instruction set
1349 bool "Loongson 2F"
1353 The Loongson 2F processor implements the MIPS III instruction set
1356 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1361 bool "Loongson 1B"
1366 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1367 Release 1 instruction set and part of the MIPS32 Release 2
1371 bool "Loongson 1C"
1376 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1377 Release 1 instruction set and part of the MIPS32 Release 2
1381 bool "MIPS32 Release 1"
1387 Choose this option to build a kernel for release 1 or later of the
1388 MIPS32 architecture. Most modern embedded systems with a 32-bit
1406 MIPS32 architecture. Most modern embedded systems with a 32-bit
1443 bool "MIPS64 Release 1"
1451 Choose this option to build a kernel for release 1 or later of the
1452 MIPS64 architecture. Many modern embedded systems with a 64-bit
1472 MIPS64 architecture. Many modern embedded systems with a 64-bit
1527 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1529 cache, IOCU/IOMMU (though might be unused depending on the system-
1554 MIPS Technologies R4300-series processors.
1563 MIPS Technologies R4000-series processors other than 4300, including
1581 MIPS Technologies R5000-series processors other than the Nevada.
1590 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1600 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1611 MIPS Technologies R10000-series processors.
1675 bool "New Loongson-3 CPU Enhancements"
1679 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1680 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1681 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1682 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1686 time. If you want a generic kernel to run on all Loongson 3 machines,
1687 please say 'N' here. If you want a high-performance kernel to run on
1688 new Loongson-3 machines only, please say 'Y' here.
1691 bool "Loongson-3 LLSC Workarounds"
1695 Loongson-3 processors have the llsc issues which require workarounds.
1701 bool "Emulate the CPUCFG instruction on older Loongson cores"
1705 Loongson-3A R4 and newer have the CPUCFG instruction available for
1707 option provides emulation of the instruction on older Loongson
1708 cores, back to Loongson-3A1000.
1757 64-bit addressing which in turn makes the PTEs 64-bit in size.
1768 bool "Loongson 2F Workarounds"
1773 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1776 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1778 Loongson 2F03 and later have fixed these issues and no workarounds
1947 # CPU may reorder R->R, R->W, W->R, W->W
1955 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2007 default 1 if CPU_MIPSR1
2057 actually benefits from 64-bit processing or if your machine has
2059 menu if your system does not support both 32-bit and 64-bit kernels.
2062 bool "32-bit kernel"
2066 Select this option if you want to build a 32-bit kernel.
2069 bool "64-bit kernel"
2072 Select this option if you want to build a 64-bit kernel.
2097 This is only used if non-zero.
2124 # Support for a MIPS32 / MIPS64 style S-caches
2186 bool "MIPS MT SMP support (1 TC on each available VPE)"
2204 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2225 bool "Dynamic FPU affinity for FP-intensive threads"
2230 bool "MIPS R2-to-R6 emulator"
2235 Choose this option if you want to run non-R6 MIPS userland code.
2238 The only reason this is a build-time option is to save ~14K from the
2410 # CPU non-features
2415 # - The `daddi' instruction fails to trap on overflow.
2419 # - The `daddiu' instruction can produce an incorrect result.
2431 # - A double-word or a variable shift may give an incorrect result
2438 # - A double-word or a variable shift may give an incorrect result
2443 # - An integer division may give an incorrect result if started in
2453 # - A double-word or a variable shift may give an incorrect result
2462 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2483 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2535 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2537 # I-cache line worth of instructions being fetched may case spurious
2543 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2552 # - Highmem only makes sense for the 32-bit kernel.
2553 # - The current highmem code will only work properly on physically indexed
2560 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2584 This option must be set if a kernel might be executed on a MIPS16-
2586 words, it makes the kernel MIPS16-tolerant.
2605 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2624 so it can be loaded someplace besides the default 1MB.
2639 adjusted, although the default of 1Mb should be ok in most cases.
2672 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2673 EVA or 64-bit. The default is 16Mb.
2700 bool "Multi-Processing support"
2707 If you say N here, the kernel will run on uni- and multiprocessor
2716 See also the SMP-HOWTO available at
2722 bool "Support for hot-pluggable CPUs"
2756 int "Maximum number of CPUs (2-256)"
2766 kernel will support. The maximum supported value is 32 for 32-bit
2767 kernel and 64 for 64-bit kernels; the minimum value which makes
2768 sense is 1 for Qemu (useful only for kernel debugging purposes)
2771 This is purely to save memory - each supported CPU adds
2891 passed to the panic-ed kernel).
2894 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2897 When this is enabled, the kernel will support use of 64-bit floating
2899 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2900 32-bit MIPS systems this support is at the cost of increasing the
2903 will require 64-bit floating point, you may wish to reduce the size
2946 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3041 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3043 <http://www.linux-mips.org/wiki/DECstation>
3087 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3100 64-bit binaries using 32-bit quantities for addressing and certain
3101 data that would normally be 64-bit. They are used in special
3108 depends on $(cc-option,-mno-branch-likely)
3110 # https://github.com/llvm/llvm-project/issues/61045