Lines Matching +full:0 +full:x0400000
57 #if CONFIG_KERNEL_BASE_ADDR == 0
59 .org 0x100
66 addi r8, r0, 0xFFFFFFFF
72 * r8 == 0 - msr instructions are implemented
73 * r8 != 0 - msr instructions are not implemented
76 msrclr r8, 0 /* clear nothing - just read msr for test */
86 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
99 ori r3, r0, (0x10000 - 4)
126 addik r5, r4, 0 /* add new space for command line */
180 or r9, r0, r0 /* TLB0 = 0 */
181 or r10, r0, r0 /* TLB1 = 0 */
183 addik r11, r12, -0x1000000
185 addik r11, r12, -0x0800000
187 addik r11, r12, -0x0400000
190 addik r11, r12, -0x0200000
192 addik r9, r0, 0x0100000 /* TLB0 must be 1MB */
193 addik r11, r12, -0x0100000
195 /* TLB1 is 0 which is setup above */
198 ori r9, r0, 0x400000 /* TLB0 is 4MB */
201 addik r9, r0, 0x1000000 /* means TLB0 is 16MB */
204 addik r2, r11, -0x0400000
207 addik r11, r11, -0x0100000
211 addik r10, r0, 0x0100000 /* means TLB1 is 1MB */
213 GT2: /* TLB0 is 0 and TLB1 will be 4MB */
215 addik r10, r0, 0x0400000 /* means TLB1 is 4MB */
219 addik r10, r0, 0x1000000 /* means TLB1 is 16MB */
223 * Configure and load two entries into TLB slots 0 and 1.
228 andi r4,r4,0xfffffc00 /* Mask off the real page number */
241 ori r30, r0, 0x200
242 andi r29, r9, 0x100000
244 addik r30, r30, 0x80
245 andi r29, r9, 0x400000
247 addik r30, r30, 0x80
248 andi r29, r9, 0x1000000
250 addik r30, r30, 0x80
252 andi r3,r3,0xfffffc00 /* Mask off the effective page number */
258 mts rtlbx,r11 /* TLB slow 0 */
271 ori r30, r0, 0x200
272 andi r29, r10, 0x100000
274 addik r30, r30, 0x80
275 andi r29, r10, 0x400000
277 addik r30, r30, 0x80
278 andi r29, r10, 0x1000000
280 addik r30, r30, 0x80
285 andi r3,r3,0xfffffc00 /* Mask off the effective page number */
323 rted r15,0 /* enables MMU */
358 rted r15,0
373 rted r17, 0 /* enable MMU and jump to start_kernel */