Lines Matching refs:MCF_MBAR
14 #define IOMEMBASE MCF_MBAR
24 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
39 #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
40 #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
41 #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
42 #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
58 #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
59 #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
64 #define MCFGPIO_PODR (MCF_MBAR + 0xA00)
65 #define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
66 #define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
67 #define MCFGPIO_SETR (MCF_MBAR + 0xA20)
68 #define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
77 #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
78 #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
79 #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
80 #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
81 #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
82 #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
87 #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
88 #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
89 #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
90 #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
91 #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
92 #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
93 #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
94 #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
95 #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
96 #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
97 #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
98 #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
112 #define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
119 #define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)