Lines Matching +full:0 +full:x00000060
12 #define CACR_DEC 0x80000000 /* Enable data cache */
13 #define CACR_DWP 0x40000000 /* Data write protection */
14 #define CACR_DESB 0x20000000 /* Enable data store buffer */
15 #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
16 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
18 #define CACR_DDCM_CP 0x02000000 /* Copyback cache */
19 #define CACR_DDCM_P 0x04000000 /* No cache, precise */
20 #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
21 #define CACR_DCINVA 0x01000000 /* Invalidate data cache */
22 #define CACR_BEC 0x00080000 /* Enable branch cache */
23 #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
24 #define CACR_IEC 0x00008000 /* Enable instruction cache */
25 #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
26 #define CACR_IDPI 0x00001000 /* Disable CPUSHL */
27 #define CACR_IHLCK 0x00000800 /* Instruction cache half lock */
28 #define CACR_IDCM 0x00000400 /* Instruction cache inhibit */
29 #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
30 #define CACR_EUSP 0x00000020 /* Enable separate user a7 */
34 #define ACR_ENABLE 0x00008000 /* Enable address */
35 #define ACR_USER 0x00000000 /* User mode access only */
36 #define ACR_SUPER 0x00002000 /* Supervisor mode only */
37 #define ACR_ANY 0x00004000 /* Match any access mode */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
39 #define ACR_CM_CP 0x00000020 /* Copyback mode */
40 #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
41 #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
42 #define ACR_CM 0x00000060 /* Cache mode mask */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
44 #define ACR_WPROTECT 0x00000004 /* Write protect */
46 #define ACR_BA(x) ((x) & 0xff000000)
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
57 #define DCACHE_SIZE 0x8000 /* data - 32k */
61 #define ICACHE_SIZE 0x2000 /* instruction - 8k */
62 #define DCACHE_SIZE 0x2000 /* data - 8k */
65 #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
107 #define ACR2_MODE 0
126 #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
127 #define ACR1_MODE 0
128 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
129 #define ACR3_MODE 0