Lines Matching +full:0 +full:x180
30 #define MCF_MBAR2 0x80000000
35 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
37 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
38 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
40 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
45 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
46 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
47 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
48 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
49 #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
50 #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
51 #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
52 #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
53 #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
55 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
56 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
58 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
59 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
61 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
62 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
63 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
64 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
65 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
66 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
67 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
68 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
69 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
71 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
72 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
73 #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
74 #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
75 #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
80 #define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
81 #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
82 #define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
83 #define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
84 #define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
85 #define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
86 #define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
87 #define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
88 #define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
97 #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
98 #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
103 #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
104 #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
109 #define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */
110 #define MCFQSPI_SIZE 0x40 /* Register set size */
127 #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */
128 #define MCFI2C_SIZE0 0x20 /* Register set size */
130 #define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base address I2C1 */
131 #define MCFI2C_SIZE1 0x20 /* Register set size */
136 #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
137 #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
138 #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
139 #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
150 #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
189 #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
190 #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
191 #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
192 #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
193 #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
194 #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
195 #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
196 #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
198 #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
199 #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
200 #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
202 #define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
203 #define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
204 #define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
231 movel #0x10000001,%a0
235 movel #0x80000001,%a1
243 moveb %d0,0x16b(%a1) /* interrupt base register */
248 movel #0x001F0021,%d0 /* disable C/I bit */
249 movel %d0,0x84(%a0) /* set CSMR0 */
255 movel 0x180(%a1),%d0 /* get current PLL value */
256 andl #0xfffffffe,%d0 /* PLL bypass first */
257 movel %d0,0x180(%a1) /* set PLL register */
266 movel #0x125a40f0,%d0 /* set for 140MHz */
267 movel %d0,0x180(%a1) /* set PLL register */
268 orl #0x1,%d0
269 movel %d0,0x180(%a1) /* set PLL register */
276 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
277 movel %d0,0x8c(%a0)
278 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
279 movel %d0,0x90(%a0)
280 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
281 movew %d0,0x96(%a0)
286 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
287 movel %d0,0x98(%a0)
288 movel #0x001f0001,%d0 /* CS2 size of 1MB */
289 movel %d0,0x9c(%a0)
290 movew #0x0080,%d0 /* CS2 = 16bit, TA */
291 movew %d0,0xa2(%a0)
293 movel #0x00107000,%d0 /* IDEconfig1 */
294 movel %d0,0x18c(%a1)
295 movel #0x000c0400,%d0 /* IDEconfig2 */
296 movel %d0,0x190(%a1)
298 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
299 orl %d0,0xc(%a1) /* function GPIO19 */
300 orl %d0,0x8(%a1) /* enable GPIO19 as output */
301 orl %d0,0x4(%a1) /* de-assert IDE reset */