include/asm/m5206sim.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	m5206sim.h -- ColdFire 5206 System Integration Module support.
26 #define	MCFSIM_ICR1		(MCF_MBAR + 0x14)	/* Intr Ctrl reg 1 */
58 #define	MCFSIM_DAR1		(MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59 #define	MCFSIM_DMR1		(MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60 #define	MCFSIM_DCR1		(MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
62 #define	MCFSIM_CSAR0		(MCF_MBAR + 0x64)	/* CS 0 Address reg */
63 #define	MCFSIM_CSMR0		(MCF_MBAR + 0x68)	/* CS 0 Mask reg */
64 #define	MCFSIM_CSCR0		(MCF_MBAR + 0x6e)	/* CS 0 Control reg */
65 #define	MCFSIM_CSAR1		(MCF_MBAR + 0x70)	/* CS 1 Address reg */
66 #define	MCFSIM_CSMR1		(MCF_MBAR + 0x74)	/* CS 1 Mask reg */
67 #define	MCFSIM_CSCR1		(MCF_MBAR + 0x7a)	/* CS 1 Control reg */
68 #define	MCFSIM_CSAR2		(MCF_MBAR + 0x7c)	/* CS 2 Address reg */
69 #define	MCFSIM_CSMR2		(MCF_MBAR + 0x80)	/* CS 2 Mask reg */
70 #define	MCFSIM_CSCR2		(MCF_MBAR + 0x86)	/* CS 2 Control reg */
71 #define	MCFSIM_CSAR3		(MCF_MBAR + 0x88)	/* CS 3 Address reg */
72 #define	MCFSIM_CSMR3		(MCF_MBAR + 0x8c)	/* CS 3 Mask reg */
73 #define	MCFSIM_CSCR3		(MCF_MBAR + 0x92)	/* CS 3 Control reg */
74 #define	MCFSIM_CSAR4		(MCF_MBAR + 0x94)	/* CS 4 Address reg */
75 #define	MCFSIM_CSMR4		(MCF_MBAR + 0x98)	/* CS 4 Mask reg */
76 #define	MCFSIM_CSCR4		(MCF_MBAR + 0x9e)	/* CS 4 Control reg */
77 #define	MCFSIM_CSAR5		(MCF_MBAR + 0xa0)	/* CS 5 Address reg */
78 #define	MCFSIM_CSMR5		(MCF_MBAR + 0xa4)	/* CS 5 Mask reg */
79 #define	MCFSIM_CSCR5		(MCF_MBAR + 0xaa)	/* CS 5 Control reg */
80 #define	MCFSIM_CSAR6		(MCF_MBAR + 0xac)	/* CS 6 Address reg */
81 #define	MCFSIM_CSMR6		(MCF_MBAR + 0xb0)	/* CS 6 Mask reg */
82 #define	MCFSIM_CSCR6		(MCF_MBAR + 0xb6)	/* CS 6 Control reg */
83 #define	MCFSIM_CSAR7		(MCF_MBAR + 0xb8)	/* CS 7 Address reg */
84 #define	MCFSIM_CSMR7		(MCF_MBAR + 0xbc)	/* CS 7 Mask reg */
85 #define	MCFSIM_CSCR7		(MCF_MBAR + 0xc2)	/* CS 7 Control reg */
101 #define	MCFDMA_BASE1		(MCF_MBAR + 0x240)	/* Base address DMA 1 */
124 #define MCFGPIO_IRQ_VECBASE	-1
125 #define MCFGPIO_IRQ_MAX		-1
141 #define	MCFSIM_TIMER1ICR	MCFSIM_ICR9	/* Timer 1 ICR */
144 #define	MCFSIM_UART1ICR		MCFSIM_ICR12	/* UART 1 ICR */
147 #define	MCFSIM_DMA1ICR		MCFSIM_ICR14	/* DMA 1 ICR */