Lines Matching +full:use +full:- +full:external +full:- +full:pwm
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
86 #define CSA_EN 0x0001 /* Chip-Select Enable */
87 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
93 #define CSA_RO 0x8000 /* Read-Only */
95 #define CSB_EN 0x0001 /* Chip-Select Enable */
96 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
106 #define CSB_RO 0x8000 /* Read-Only */
108 #define CSC_EN 0x0001 /* Chip-Select Enable */
109 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
119 #define CSC_RO 0x8000 /* Read-Only */
121 #define CSD_EN 0x0001 /* Chip-Select Enable */
122 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
134 #define CSD_RO 0x8000 /* Read-Only */
137 * Emulation Chip-Select Register
147 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
165 /* '328-compatible definitions */
194 * 0xFFFFF3xx -- Interrupt Controller
239 #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
240 #define INT0_IRQ_NUM 8 /* External INT0 */
241 #define INT1_IRQ_NUM 9 /* External INT1 */
242 #define INT2_IRQ_NUM 10 /* External INT2 */
243 #define INT3_IRQ_NUM 11 /* External INT3 */
245 #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
257 /* '328-compatible definitions */
271 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
272 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
273 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
274 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
275 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
284 /* '328-compatible definitions */
300 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
301 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
302 #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
303 #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
304 #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
313 /* '328-compatible definitions */
329 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
330 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
331 #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
332 #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
333 #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
342 /* '328-compatible definitions */
348 * 0xFFFFF4xx -- Parallel Ports
357 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
370 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
380 #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
381 #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
382 #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
383 #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
384 #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
385 #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
386 #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
387 #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
394 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
404 #define PC_LD0 0x01 /* Use LD0 as PC[0] */
405 #define PC_LD1 0x02 /* Use LD1 as PC[1] */
406 #define PC_LD2 0x04 /* Use LD2 as PC[2] */
407 #define PC_LD3 0x08 /* Use LD3 as PC[3] */
408 #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
409 #define PC_LLP 0x20 /* Use LLP as PC[5] */
410 #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
411 #define PC_LACD 0x80 /* Use LACD as PC[7] */
418 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
436 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
437 #define PD_INT1 0x02 /* Use INT1 as PD[1] */
438 #define PD_INT2 0x04 /* Use INT2 as PD[2] */
439 #define PD_INT3 0x08 /* Use INT3 as PD[3] */
440 #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
441 #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
442 #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
443 #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
450 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
460 #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
461 #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
462 #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
463 #define PE_DWE 0x08 /* Use DWE as PE[3] */
464 #define PE_RXD 0x10 /* Use RXD as PE[4] */
465 #define PE_TXD 0x20 /* Use TXD as PE[5] */
466 #define PE_RTS 0x40 /* Use RTS as PE[6] */
467 #define PE_CTS 0x80 /* Use CTS as PE[7] */
474 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
484 #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
485 #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
486 #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
487 #define PF_A20 0x08 /* Use A20 as PF[3] */
488 #define PF_A21 0x10 /* Use A21 as PF[4] */
489 #define PF_A22 0x20 /* Use A22 as PF[5] */
490 #define PF_A23 0x40 /* Use A23 as PF[6] */
491 #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
498 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
508 #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
509 #define PG_A0 0x02 /* Use A0 as PG[1] */
510 #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
511 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
512 #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
513 #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
520 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
535 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
545 #define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
546 #define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
547 #define PK_R_W 0x02 /* Use R/W as PK[1] */
548 #define PK_LDS 0x04 /* Use /LDS as PK[2] */
549 #define PK_UDS 0x08 /* Use /UDS as PK[3] */
550 #define PK_LD4 0x10 /* Use LD4 as PK[4] */
551 #define PK_LD5 0x20 /* Use LD5 as PK[5] */
552 #define PK_LD6 0x40 /* Use LD6 as PK[6] */
553 #define PK_LD7 0x80 /* Use LD7 as PK[7] */
557 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
567 #define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
568 #define PJ_MISO 0x02 /* Use MISO as PJ[1] */
569 #define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
570 #define PJ_SS 0x08 /* Use SS as PJ[3] */
571 #define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
572 #define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
573 #define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
574 #define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
581 #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
591 #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
592 #define PM_SDCE 0x02 /* Use SDCE as PM[1] */
593 #define PM_DQMH 0x04 /* Use DQMH as PM[2] */
594 #define PM_DQML 0x08 /* Use DQML as PM[3] */
595 #define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
596 #define PM_DMOE 0x20 /* Use DMOE as PM[5] */
600 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
605 * PWM Control Register
614 #define PWMC_EN 0x0010 /* Enable PWM */
622 /* '328-compatible definitions */
626 * PWM Sample Register
632 * PWM Period Register
638 * PWM Counter Register
645 * 0xFFFFF6xx -- General-Purpose Timer
667 #define TCTL_FRR 0x0010 /* Free-Run Mode */
669 /* '328-compatible definitions */
679 /* '328-compatible definitions */
689 /* '328-compatible definitions */
699 /* '328-compatible definitions */
709 /* '328-compatible definitions */
722 /* '328-compatible definitions */
728 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
755 /* '328-compatible definitions */
761 * 0xFFFFF9xx -- UART
776 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
780 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
789 /* '328-compatible definitions */
808 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
832 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
855 /* '328-compatible definitions */
868 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
879 * UART Non-integer Prescaler Register
888 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
920 * 0xFFFFFAxx -- LCD Controller
930 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
944 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
952 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
1002 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
1047 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
1052 /* '328-compatible definitions */
1094 * PWM Contrast Control Register
1109 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1160 /* '328-compatible definitions */
1171 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1173 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1175 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1192 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1194 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1196 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1235 * 0xFFFFFCxx -- DRAM Controller
1271 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1275 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1293 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1346 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */