include/asm/MC68VZ328.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5  * Copyright (c) 2000-2001	Lineo Inc. <www.lineo.com>
6  * Copyright (c) 2000-2001	Lineo Canada Corp. <www.lineo.ca>
9  * Based on include/asm-m68knommu/MC68332.h
29  * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
42 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
45 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
55  * 0xFFFFF1xx -- Chip-Select logic
86 #define CSA_EN		0x0001		/* Chip-Select Enable */
87 #define CSA_SIZ_MASK	0x000e		/* Chip-Select Size */
91 #define CSA_BSW		0x0080		/* Data Bus Width */
93 #define CSA_RO		0x8000		/* Read-Only */
95 #define CSB_EN		0x0001		/* Chip-Select Enable */
96 #define CSB_SIZ_MASK	0x000e		/* Chip-Select Size */
100 #define CSB_BSW		0x0080		/* Data Bus Width */
106 #define CSB_RO		0x8000		/* Read-Only */
108 #define CSC_EN		0x0001		/* Chip-Select Enable */
109 #define CSC_SIZ_MASK	0x000e		/* Chip-Select Size */
113 #define CSC_BSW		0x0080		/* Data Bus Width */
119 #define CSC_RO		0x8000		/* Read-Only */
121 #define CSD_EN		0x0001		/* Chip-Select Enable */
122 #define CSD_SIZ_MASK	0x000e		/* Chip-Select Size */
126 #define CSD_BSW		0x0080		/* Data Bus Width */
134 #define CSD_RO		0x8000		/* Read-Only */
137  * Emulation Chip-Select Register
147  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
165 /* '328-compatible definitions */
188 #define PCTRL_WIDTH_MASK	0x1f	/* CPU Clock bursts width */
194  * 0xFFFFF3xx -- Interrupt Controller
233 #define TMR_IRQ_NUM	1	/* Timer 1 interrupt */
235 #define	WDT_IRQ_NUM	3	/* Watchdog Timer interrupt */
237 #define TMR2_IRQ_NUM	5	/* Timer 2 interrupt */
239 #define PWM1_IRQ_NUM	7	/* Pulse-Width Modulator 1 int. */
245 #define PWM2_IRQ_NUM	13	/* Pulse-Width Modulator 1 int. */
252 #define SAM_IRQ_NUM	22	/* Sampling Timer for RTC */
257 /* '328-compatible definitions */
266 #define	IMR_MTMR	(1 << TMR_IRQ_NUM)	/* Mask Timer interrupt */
268 #define	IMR_MWDT	(1 << WDT_IRQ_NUM)	/* Mask Watchdog Timer interrupt */
271 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
281 #define IMR_MSAM	(1 << SAM_IRQ_NUM)	/* Mask Sampling Timer for RTC */
284 /* '328-compatible definitions */
295 #define	ISR_TMR		(1 << TMR_IRQ_NUM)	/* Timer interrupt */
297 #define	ISR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
300 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator interrupt */
310 #define ISR_SAM		(1 << SAM_IRQ_NUM)	/* Sampling Timer for RTC */
313 /* '328-compatible definitions */
324 #define	IPR_TMR		(1 << TMR_IRQ_NUM)	/* Timer interrupt */
326 #define	IPR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
329 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator interrupt */
339 #define IPR_SAM		(1 << SAM_IRQ_NUM)	/* Sampling Timer for RTC */
342 /* '328-compatible definitions */
348  * 0xFFFFF4xx -- Parallel Ports
357 #define PAPUEN_ADDR	0xfffff402		/* Port A Pull-Up enable reg */
370 #define PBPUEN_ADDR	0xfffff40a		/* Port B Pull-Up enable reg */
394 #define PCPDEN_ADDR	0xfffff412		/* Port C Pull-Down enb. reg */
418 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
450 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
474 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
498 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
520 #define PJPUEN_ADDR	0xfffff43A		/* Port J Pull-Up enb. reg */
535 #define PKPUEN_ADDR	0xfffff442		/* Port K Pull-Up enb. reg */
557 #define PJPUEN_ADDR	0xfffff43A		/* Port J Pull-Up enable reg */
581 #define PMPUEN_ADDR	0xfffff44a		/* Port M Pull-Up enable reg */
600  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
622 /* '328-compatible definitions */
645  * 0xFFFFF6xx -- General-Purpose Timer
650  * Timer Control register
655 #define	TCTL_TEN		0x0001	/* Timer Enable  */
667 #define TCTL_FRR		0x0010	/* Free-Run Mode */
669 /* '328-compatible definitions */
674  * Timer Prescaler Register
679 /* '328-compatible definitions */
684  * Timer Compare Register
689 /* '328-compatible definitions */
694  * Timer Capture register
699 /* '328-compatible definitions */
704  * Timer Counter Register
709 /* '328-compatible definitions */
714  * Timer Status Register
722 /* '328-compatible definitions */
728  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
755 /* '328-compatible definitions */
761  * 0xFFFFF9xx -- UART
776 #define USTCNT_RXHE	0x0010	/* Receiver Half-Full Interrupt Enable */
780 #define USTCNT_8_7	0x0100	/* Eight or seven-bit transmission */
789 /* '328-compatible definitions */
808 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
832 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
855 /* '328-compatible definitions */
868 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
879  * UART Non-integer Prescaler Register
888 #define NIPR_PRE_SEL		0x8000	/* Non-integer prescaler select */
920  * 0xFFFFFAxx -- LCD Controller
930 #define LSSA_SSA_MASK	0x1ffffffe	/* Bits 0 and 29-31 are reserved */
933  * LCD Virtual Page Width Register
939  * LCD Screen Width Register (not compatible with '328 !!!)
944 #define LXMAX_XM_MASK	0x02f0		/* Bits 0-3 and 10-15 are reserved */
952 #define LYMAX_YM_MASK	0x01ff		/* Bits 9-15 are reserved */
976  * LCD Cursor Width and Heigth Register
983 #define LCWCH_CW_MASK	0x1f00		/* Cursor Width */
1002 #define LPICF_GS_MASK	 0x03	 /* Gray-Scale Mode */
1006 #define LPICF_PBSIZ_MASK 0x0c	/* Panel Bus Width */
1047 #define LCKCON_DWS_MASK	 0x0f	/* Display Wait-State */
1049 #define LCKCON_DWIDTH	 0x40	/* Display Memory Width  */
1052 /* '328-compatible definitions */
1099 #define PWMR_PW_MASK	0x00ff	/* Pulse Width */
1109  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1140  * Watchdog Timer Register
1160 /* '328-compatible definitions */
1171 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1173 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1175 #define RTCISR_HR	0x0020	/* 1-hour interrupt has occurred */
1192 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1194 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */
1196 #define RTCIENR_HR	0x0020	/* 1-hour interrupt enable */
1235  * 0xFFFFFCxx -- DRAM Controller
1271 #define DRAMC_LPR	   0x0004	/* Low-Power Refresh Enable */
1275 #define DRAMC_WS_MASK	   0x00c0	/* Wait-states */
1284 #define DRAMC_CLK	   0x0800	/* Refresh Timer Clock source select */
1293  * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1346 #define ICEMSR_BRKIRQ	0x0002	/* A-Line Vector Fetch Detected */