Lines Matching +full:data +full:- +full:ready +full:- +full:hiz
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
86 #define CSA_EN 0x0001 /* Chip-Select Enable */
87 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
91 #define CSA_BSW 0x0080 /* Data Bus Width */
93 #define CSA_RO 0x8000 /* Read-Only */
95 #define CSB_EN 0x0001 /* Chip-Select Enable */
96 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
100 #define CSB_BSW 0x0080 /* Data Bus Width */
106 #define CSB_RO 0x8000 /* Read-Only */
108 #define CSC_EN 0x0001 /* Chip-Select Enable */
109 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
113 #define CSC_BSW 0x0080 /* Data Bus Width */
119 #define CSC_RO 0x8000 /* Read-Only */
121 #define CSD_EN 0x0001 /* Chip-Select Enable */
122 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
126 #define CSD_BSW 0x0080 /* Data Bus Width */
134 #define CSD_RO 0x8000 /* Read-Only */
137 * Emulation Chip-Select Register
147 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
165 /* '328-compatible definitions */
194 * 0xFFFFF3xx -- Interrupt Controller
239 #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
245 #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
257 /* '328-compatible definitions */
271 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
284 /* '328-compatible definitions */
300 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
313 /* '328-compatible definitions */
329 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
342 /* '328-compatible definitions */
348 * 0xFFFFF4xx -- Parallel Ports
356 #define PADATA_ADDR 0xfffff401 /* Port A data register */
357 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
369 #define PBDATA_ADDR 0xfffff409 /* Port B data register */
370 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
393 #define PCDATA_ADDR 0xfffff411 /* Port C data register */
394 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
417 #define PDDATA_ADDR 0xfffff419 /* Port D data register */
418 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
449 #define PEDATA_ADDR 0xfffff421 /* Port E data register */
450 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
473 #define PFDATA_ADDR 0xfffff429 /* Port F data register */
474 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
497 #define PGDATA_ADDR 0xfffff431 /* Port G data register */
498 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
511 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
519 #define PJDATA_ADDR 0xfffff439 /* Port J data register */
520 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
534 #define PKDATA_ADDR 0xfffff441 /* Port K data register */
535 #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
556 #define PJDATA_ADDR 0xfffff439 /* Port J data register */
557 #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
580 #define PMDATA_ADDR 0xfffff449 /* Port M data register */
581 #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
600 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
622 /* '328-compatible definitions */
645 * 0xFFFFF6xx -- General-Purpose Timer
667 #define TCTL_FRR 0x0010 /* Free-Run Mode */
669 /* '328-compatible definitions */
679 /* '328-compatible definitions */
689 /* '328-compatible definitions */
699 /* '328-compatible definitions */
709 /* '328-compatible definitions */
722 /* '328-compatible definitions */
728 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
733 * SPIM Data Register
747 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
752 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
755 /* '328-compatible definitions */
761 * 0xFFFFF9xx -- UART
775 #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
776 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
779 #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
780 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
789 /* '328-compatible definitions */
808 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
824 #define URX_RXDATA_MASK 0x00ff /* Received data */
830 #define URX_OLD_DATA 0x1000 /* Old data in FIFO */
831 #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
832 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
844 #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
855 /* '328-compatible definitions */
868 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
879 * UART Non-integer Prescaler Register
888 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
920 * 0xFFFFFAxx -- LCD Controller
930 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
944 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
952 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
1002 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
1047 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
1052 /* '328-compatible definitions */
1109 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1160 /* '328-compatible definitions */
1171 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1173 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1175 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1192 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1194 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1196 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1235 * 0xFFFFFCxx -- DRAM Controller
1271 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1275 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1293 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1315 #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
1324 #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1346 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */