Lines Matching +full:use +full:- +full:external +full:- +full:pwm
1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
91 #define CSA_RO 0x8000 /* Read-Only */
93 #define CSB_EN 0x0001 /* Chip-Select Enable */
94 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
104 #define CSB_RO 0x8000 /* Read-Only */
106 #define CSC_EN 0x0001 /* Chip-Select Enable */
107 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
117 #define CSC_RO 0x8000 /* Read-Only */
119 #define CSD_EN 0x0001 /* Chip-Select Enable */
120 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
132 #define CSD_RO 0x8000 /* Read-Only */
135 * Emulation Chip-Select Register
145 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
163 /* '328-compatible definitions */
192 * 0xFFFFF3xx -- Interrupt Controller
236 #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
237 #define INT0_IRQ_NUM 8 /* External INT0 */
238 #define INT1_IRQ_NUM 9 /* External INT1 */
239 #define INT2_IRQ_NUM 10 /* External INT2 */
240 #define INT3_IRQ_NUM 11 /* External INT3 */
249 /* '328-compatible definitions */
262 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
263 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
264 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
265 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
266 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
275 /* '328-compatible definitions */
291 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
292 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
293 #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
294 #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
295 #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
304 /* '328-compatible definitions */
320 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
321 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
322 #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
323 #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
324 #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
333 /* '328-compatible definitions */
339 * 0xFFFFF4xx -- Parallel Ports
348 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
361 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
371 #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
372 #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
373 #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
374 #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
375 #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
376 #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
377 #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
378 #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
385 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
395 #define PC_LD0 0x01 /* Use LD0 as PC[0] */
396 #define PC_LD1 0x02 /* Use LD1 as PC[1] */
397 #define PC_LD2 0x04 /* Use LD2 as PC[2] */
398 #define PC_LD3 0x08 /* Use LD3 as PC[3] */
399 #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
400 #define PC_LLP 0x20 /* Use LLP as PC[5] */
401 #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
402 #define PC_LACD 0x80 /* Use LACD as PC[7] */
409 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
427 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
428 #define PD_INT1 0x02 /* Use INT1 as PD[1] */
429 #define PD_INT2 0x04 /* Use INT2 as PD[2] */
430 #define PD_INT3 0x08 /* Use INT3 as PD[3] */
431 #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
432 #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
433 #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
434 #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
441 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
451 #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
452 #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
453 #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
454 #define PE_DWE 0x08 /* Use DWE as PE[3] */
455 #define PE_RXD 0x10 /* Use RXD as PE[4] */
456 #define PE_TXD 0x20 /* Use TXD as PE[5] */
457 #define PE_RTS 0x40 /* Use RTS as PE[6] */
458 #define PE_CTS 0x80 /* Use CTS as PE[7] */
465 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
475 #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
476 #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
477 #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
478 #define PF_A20 0x08 /* Use A20 as PF[3] */
479 #define PF_A21 0x10 /* Use A21 as PF[4] */
480 #define PF_A22 0x20 /* Use A22 as PF[5] */
481 #define PF_A23 0x40 /* Use A23 as PF[6] */
482 #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
489 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
499 #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
500 #define PG_A0 0x02 /* Use A0 as PG[1] */
501 #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
502 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
503 #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
504 #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
508 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
513 * PWM Control Register
522 #define PWMC_EN 0x0010 /* Enable PWM */
530 /* '328-compatible definitions */
534 * PWM Sample Register
540 * PWM Period Register
546 * PWM Counter Register
553 * 0xFFFFF6xx -- General-Purpose Timer
575 #define TCTL_FRR 0x0010 /* Free-Run Mode */
577 /* '328-compatible definitions */
587 /* '328-compatible definitions */
597 /* '328-compatible definitions */
607 /* '328-compatible definitions */
617 /* '328-compatible definitions */
630 /* '328-compatible definitions */
636 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
663 /* '328-compatible definitions */
669 * 0xFFFFF9xx -- UART
683 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
687 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
696 /* '328-compatible definitions */
715 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
739 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
762 /* '328-compatible definitions */
775 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
786 * UART Non-integer Prescaler Register
795 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
825 * 0xFFFFFAxx -- LCD Controller
835 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
849 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
857 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
907 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
952 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
957 /* '328-compatible definitions */
999 * PWM Contrast Control Register
1014 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1065 /* '328-compatible definitions */
1076 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1078 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1080 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1097 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1099 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1101 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1140 * 0xFFFFFCxx -- DRAM Controller
1176 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1180 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1198 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1251 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */