include/asm/MC68328.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8  * Based on include/asm-m68knommu/MC68332.h
26  * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
39 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
42 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
52  * 0xFFFFF1xx -- Chip-Select logic
58  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK  0xfff0	/* Group Base Address (bits 31-20) */
91 #define GRMMASK_GMA_MASK 0xfffff0	/* Group Base Mask (bits 31-20) */
94  * Chip-Select Option Registers (group A)
108 #define CSA_RO		0x00000008	/* Read-Only */
109 #define CSA_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
112 #define CSA_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
116  * Chip-Select Option Registers (group B)
130 #define CSB_RO		0x00000008	/* Read-Only */
131 #define CSB_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
134 #define CSB_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
138  * Chip-Select Option Registers (group C)
152 #define CSC_RO		0x00000008	/* Read-Only */
153 #define CSC_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
156 #define CSC_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
160  * Chip-Select Option Registers (group D)
174 #define CSD_RO		0x00000008	/* Read-Only */
175 #define CSD_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
178 #define CSD_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
183  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
200 /* 'EZ328-compatible definitions */
225 #define PCTRL_STOP		0x40	/* Enter power-save mode immediately */
230  * 0xFFFFF3xx -- Interrupt Controller
273 #define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
274 #define	INT0_IRQ_NUM	8	/* External INT0 */
275 #define	INT1_IRQ_NUM	9	/* External INT1 */
276 #define	INT2_IRQ_NUM	10	/* External INT2 */
277 #define	INT3_IRQ_NUM	11	/* External INT3 */
278 #define	INT4_IRQ_NUM	12	/* External INT4 */
279 #define	INT5_IRQ_NUM	13	/* External INT5 */
280 #define	INT6_IRQ_NUM	14	/* External INT6 */
281 #define	INT7_IRQ_NUM	15	/* External INT7 */
291 /* '328-compatible definitions */
304 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
305 #define	IMR_MINT0	(1 << INT0_IRQ_NUM)	/* Mask External INT0 */
306 #define	IMR_MINT1	(1 << INT1_IRQ_NUM)	/* Mask External INT1 */
307 #define	IMR_MINT2	(1 << INT2_IRQ_NUM)	/* Mask External INT2 */
308 #define	IMR_MINT3	(1 << INT3_IRQ_NUM)	/* Mask External INT3 */
309 #define	IMR_MINT4	(1 << INT4_IRQ_NUM)	/* Mask External INT4 */
310 #define	IMR_MINT5	(1 << INT5_IRQ_NUM)	/* Mask External INT5 */
311 #define	IMR_MINT6	(1 << INT6_IRQ_NUM)	/* Mask External INT6 */
312 #define	IMR_MINT7	(1 << INT7_IRQ_NUM)	/* Mask External INT7 */
322 /* 'EZ328-compatible definitions */
327  * Interrupt Wake-Up Enable Register
338 #define IWR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
339 #define	IWR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
340 #define	IWR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
341 #define	IWR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
342 #define	IWR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
343 #define	IWR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
344 #define	IWR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
345 #define	IWR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
346 #define	IWR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
368 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
369 #define	ISR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
370 #define	ISR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
371 #define	ISR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
372 #define	ISR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
373 #define	ISR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
374 #define	ISR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
375 #define	ISR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
376 #define	ISR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
386 /* 'EZ328-compatible definitions */
402 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
403 #define	IPR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
404 #define	IPR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
405 #define	IPR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
406 #define	IPR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
407 #define	IPR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
408 #define	IPR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
409 #define	IPR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
410 #define	IPR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
420 /* 'EZ328-compatible definitions */
426  * 0xFFFFF4xx -- Parallel Ports
442 #define PA_A(x)		PA((x) - 16)	/* This is specific to PA only! */
444 #define PA_A16		PA(0)		/* Use A16 as PA(0) */
445 #define PA_A17		PA(1)		/* Use A17 as PA(1) */
446 #define PA_A18		PA(2)		/* Use A18 as PA(2) */
447 #define PA_A19		PA(3)		/* Use A19 as PA(3) */
448 #define PA_A20		PA(4)		/* Use A20 as PA(4) */
449 #define PA_A21		PA(5)		/* Use A21 as PA(5) */
450 #define PA_A22		PA(6)		/* Use A22 as PA(6) */
451 #define PA_A23		PA(7)		/* Use A23 as PA(7) */
467 #define PB_D0		PB(0)		/* Use D0 as PB(0) */
468 #define PB_D1		PB(1)		/* Use D1 as PB(1) */
469 #define PB_D2		PB(2)		/* Use D2 as PB(2) */
470 #define PB_D3		PB(3)		/* Use D3 as PB(3) */
471 #define PB_D4		PB(4)		/* Use D4 as PB(4) */
472 #define PB_D5		PB(5)		/* Use D5 as PB(5) */
473 #define PB_D6		PB(6)		/* Use D6 as PB(6) */
474 #define PB_D7		PB(7)		/* Use D7 as PB(7) */
489 #define PC_WE		PC(6)		/* Use WE    as PC(6) */
490 #define PC_DTACK	PC(5)		/* Use DTACK as PC(5) */
491 #define PC_IRQ7		PC(4)		/* Use IRQ7  as PC(4) */
492 #define PC_LDS		PC(2)		/* Use LDS   as PC(2) */
493 #define PC_UDS		PC(1)		/* Use UDS   as PC(1) */
494 #define PC_MOCLK	PC(0)		/* Use MOCLK as PC(0) */
501 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
516 #define PD_KB0		PD(0)	/* Use KB0 as PD(0) */
517 #define PD_KB1		PD(1)	/* Use KB1 as PD(1) */
518 #define PD_KB2		PD(2)	/* Use KB2 as PD(2) */
519 #define PD_KB3		PD(3)	/* Use KB3 as PD(3) */
520 #define PD_KB4		PD(4)	/* Use KB4 as PD(4) */
521 #define PD_KB5		PD(5)	/* Use KB5 as PD(5) */
522 #define PD_KB6		PD(6)	/* Use KB6 as PD(6) */
523 #define PD_KB7		PD(7)	/* Use KB7 as PD(7) */
530 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
540 #define PE_CSA1		PE(1)	/* Use CSA1 as PE(1) */
541 #define PE_CSA2		PE(2)	/* Use CSA2 as PE(2) */
542 #define PE_CSA3		PE(3)	/* Use CSA3 as PE(3) */
543 #define PE_CSB0		PE(4)	/* Use CSB0 as PE(4) */
544 #define PE_CSB1		PE(5)	/* Use CSB1 as PE(5) */
545 #define PE_CSB2		PE(6)	/* Use CSB2 as PE(6) */
546 #define PE_CSB3		PE(7)	/* Use CSB3 as PE(7) */
553 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
562 #define PF_A(x)		PF((x) - 24)	/* This is Port F specific only */
564 #define PF_A24		PF(0)	/* Use A24 as PF(0) */
565 #define PF_A25		PF(1)	/* Use A25 as PF(1) */
566 #define PF_A26		PF(2)	/* Use A26 as PF(2) */
567 #define PF_A27		PF(3)	/* Use A27 as PF(3) */
568 #define PF_A28		PF(4)	/* Use A28 as PF(4) */
569 #define PF_A29		PF(5)	/* Use A29 as PF(5) */
570 #define PF_A30		PF(6)	/* Use A30 as PF(6) */
571 #define PF_A31		PF(7)	/* Use A31 as PF(7) */
578 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
588 #define PG_UART_TXD	PG(0)	/* Use UART_TXD as PG(0) */
589 #define PG_UART_RXD	PG(1)	/* Use UART_RXD as PG(1) */
590 #define PG_PWMOUT	PG(2)	/* Use PWMOUT   as PG(2) */
591 #define PG_TOUT2	PG(3)   /* Use TOUT2    as PG(3) */
592 #define PG_TIN2		PG(4)	/* Use TIN2     as PG(4) */
593 #define PG_TOUT1	PG(5)   /* Use TOUT1    as PG(5) */
594 #define PG_TIN1		PG(6)	/* Use TIN1     as PG(6) */
595 #define PG_RTCOUT	PG(7)	/* Use RTCOUT   as PG(7) */
610 #define PJ_CSD3		PJ(7)	/* Use CSD3 as PJ(7) */
617 #define PKPUEN_ADDR	0xfffff442		/* Port K Pull-Up enable reg */
632 #define PMPUEN_ADDR	0xfffff43a		/* Port M Pull-Up enable reg */
644  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
649  * PWM Control Register
656 #define PWMC_PWMEN		0x0010	/* Enable PWM */
657 #define PMNC_POL		0x0020	/* PWM Output Bit Polarity */
658 #define PWMC_PIN		0x0080	/* Current PWM output pin status */
663 /* 'EZ328-compatible definitions */
667  * PWM Period Register
673  * PWM Width Register
679  * PWM Counter Register
686  * 0xFFFFF6xx -- General-Purpose Timers
710 #define TCTL_FRR		0x0010	/* Free-Run Mode */
712 /* 'EZ328-compatible definitions */
724 /* 'EZ328-compatible definitions */
736 /* 'EZ328-compatible definitions */
748 /* 'EZ328-compatible definitions */
760 /* 'EZ328-compatible definitions */
775 /* 'EZ328-compatible definitions */
803  * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
816 #define SPISR_DATA_MASK	 0x00ff	/* Shifted data from the external device */
829  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
856 /* 'EZ328-compatible definitions */
861  * 0xFFFFF9xx -- UART
875 #define USTCNT_RXHALFEN		0x0010	/* Receiver Half-Full Int Enable */
879 #define USTCNT_8_7		0x0100	/* Eight or seven-bit transmission */
888 /* 'EZ328-compatible definitions */
907 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
933 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
955 /* 'EZ328-compatible definitions */
968 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
1003  * 0xFFFFFAxx -- LCD Controller
1027 #define LXMAX_XM_MASK	0x02ff		/* Bits 0-3 are reserved */
1035 #define LYMAX_YM_MASK	0x02ff		/* Bits 10-15 are reserved */
1085 #define LPICF_GS_MASK	 0x01	 /* Gray-Scale Mode */
1130 #define LCKCON_DWS_MASK	 0x3c	/* Display Wait-State */
1135 /* 'EZ328-compatible definitions */
1192  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1231 /* 'EZ328-compatible definitions */
1242 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1244 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1254 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1256 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */