include/asm/MC68328.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8  * Based on include/asm-m68knommu/MC68332.h
26  * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
39 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
42 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
52  * 0xFFFFF1xx -- Chip-Select logic
58  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK  0xfff0	/* Group Base Address (bits 31-20) */
91 #define GRMMASK_GMA_MASK 0xfffff0	/* Group Base Mask (bits 31-20) */
94  * Chip-Select Option Registers (group A)
108 #define CSA_RO		0x00000008	/* Read-Only */
109 #define CSA_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
111 #define CSA_BUSW	0x00010000	/* Bus Width Select */
112 #define CSA_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
116  * Chip-Select Option Registers (group B)
130 #define CSB_RO		0x00000008	/* Read-Only */
131 #define CSB_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
133 #define CSB_BUSW	0x00010000	/* Bus Width Select */
134 #define CSB_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
138  * Chip-Select Option Registers (group C)
152 #define CSC_RO		0x00000008	/* Read-Only */
153 #define CSC_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
155 #define CSC_BUSW	0x00010000	/* Bus Width Select */
156 #define CSC_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
160  * Chip-Select Option Registers (group D)
174 #define CSD_RO		0x00000008	/* Read-Only */
175 #define CSD_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
177 #define CSD_BUSW	0x00010000	/* Bus Width Select */
178 #define CSD_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
183  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
200 /* 'EZ328-compatible definitions */
223 #define PCTRL_WIDTH_MASK	0x1f	/* CPU Clock bursts width */
225 #define PCTRL_STOP		0x40	/* Enter power-save mode immediately */
230  * 0xFFFFF3xx -- Interrupt Controller
268 #define	TMR2_IRQ_NUM	1	/* Timer 2 interrupt */
270 #define	WDT_IRQ_NUM	3	/* Watchdog Timer interrupt */
273 #define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
288 #define TMR1_IRQ_NUM	22	/* Timer 1 interrupt */
291 /* '328-compatible definitions */
299 #define	IMR_MTMR2	(1 << TMR2_IRQ_NUM)	/* Mask Timer 2 interrupt */
301 #define	IMR_MWDT	(1 << WDT_IRQ_NUM)	/* Mask Watchdog Timer interrupt */
304 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
319 #define IMR_MTMR1	(1 << TMR1_IRQ_NUM)	/* Mask Timer 1 interrupt */
322 /* 'EZ328-compatible definitions */
327  * Interrupt Wake-Up Enable Register
333 #define	IWR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
335 #define	IWR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
338 #define IWR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
353 #define IWR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
363 #define	ISR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
365 #define	ISR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
368 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
383 #define ISR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
386 /* 'EZ328-compatible definitions */
397 #define	IPR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
399 #define	IPR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
402 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
417 #define IPR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
420 /* 'EZ328-compatible definitions */
426  * 0xFFFFF4xx -- Parallel Ports
442 #define PA_A(x)		PA((x) - 16)	/* This is specific to PA only! */
501 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
530 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
553 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
562 #define PF_A(x)		PF((x) - 24)	/* This is Port F specific only */
578 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
617 #define PKPUEN_ADDR	0xfffff442		/* Port K Pull-Up enable reg */
632 #define PMPUEN_ADDR	0xfffff43a		/* Port M Pull-Up enable reg */
644  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
663 /* 'EZ328-compatible definitions */
673  * PWM Width Register
686  * 0xFFFFF6xx -- General-Purpose Timers
691  * Timer Unit 1 and 2 Control Registers
698 #define	TCTL_TEN		0x0001	/* Timer Enable  */
710 #define TCTL_FRR		0x0010	/* Free-Run Mode */
712 /* 'EZ328-compatible definitions */
717  * Timer Unit 1 and 2 Prescaler Registers
724 /* 'EZ328-compatible definitions */
729  * Timer Unit 1 and 2 Compare Registers
736 /* 'EZ328-compatible definitions */
741  * Timer Unit 1 and 2 Capture Registers
748 /* 'EZ328-compatible definitions */
753  * Timer Unit 1 and 2 Counter Registers
760 /* 'EZ328-compatible definitions */
765  * Timer Unit 1 and 2 Status Registers
775 /* 'EZ328-compatible definitions */
803  * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
829  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
856 /* 'EZ328-compatible definitions */
861  * 0xFFFFF9xx -- UART
875 #define USTCNT_RXHALFEN		0x0010	/* Receiver Half-Full Int Enable */
879 #define USTCNT_8_7		0x0100	/* Eight or seven-bit transmission */
888 /* 'EZ328-compatible definitions */
907 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
933 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
955 /* 'EZ328-compatible definitions */
968 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
1003  * 0xFFFFFAxx -- LCD Controller
1016  * LCD Virtual Page Width Register
1022  * LCD Screen Width Register (not compatible with 'EZ328 !!!)
1027 #define LXMAX_XM_MASK	0x02ff		/* Bits 0-3 are reserved */
1035 #define LYMAX_YM_MASK	0x02ff		/* Bits 10-15 are reserved */
1059  * LCD Cursor Width and Heigth Register
1066 #define LCWCH_CW_MASK	0x1f00		/* Cursor Width */
1085 #define LPICF_GS_MASK	 0x01	 /* Gray-Scale Mode */
1088 #define LPICF_PBSIZ_MASK 0x06	/* Panel Bus Width */
1129 #define LCKCON_DWIDTH	 0x02	/* Display Memory Width  */
1130 #define LCKCON_DWS_MASK	 0x3c	/* Display Wait-State */
1135 /* 'EZ328-compatible definitions */
1192  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1231 /* 'EZ328-compatible definitions */
1242 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1244 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1254 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1256 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */