ifpsp060/src/ilsp.S

3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
63 #	_060LSP__idivu64_(): Emulate 64-bit unsigned div instruction.	#
64 #	_060LSP__idivs64_(): Emulate 64-bit signed div instruction.	#
68 #	64-bit divide instruction.					#
75 #	0x8(sp)  = hi(dividend)						#
85 # sign info for later. Separate out special cases like divide-by-zero	#
86 # or 32-bit divides if possible. Else, use a special math algorithm	#
90 # zero, then perform a divide-by-zero using a 16-bit implemented	#
96 set	POSNEG,		-1
97 set	NDIVISOR,	-2
98 set	NDIVIDEND,	-3
99 set	DDSECOND,	-4
100 set	DDNORMAL,	-8
101 set	DDQUOTIENT,	-12
102 set	DIV64_CC,	-16
110 	link.w		%a6,&-16
111 	movm.l		&0x3f00,-(%sp)		# save d2-d7
112 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
125 	link.w		%a6,&-16
126 	movm.l		&0x3f00,-(%sp)		# save d2-d7
127 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
138 	mov.l		0xc(%a6), %d5		# get dividend hi
155 	tst.l		%d5			# chk sign of hi(dividend)
164 #	- is (dividend == 0) ?
165 #	- is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
167 	tst.l		%d5			# is (hi(dividend) == 0)
186 #	- is hi(dividend) >= divisor ? if yes, then overflow
207 # 0x80000000 is the largest number representable as a 32-bit negative
209 	cmpi.l		%d6, &0x80000000	# will (-quot) fit in 32 bits?
212 	neg.l		%d6			# make (-quot) 2's comp
235 	movm.l		(%sp)+,&0x00fc		# restore d2-d7
243 	mov.l		0xc(%a6), %d5		# get dividend hi
260 	movm.l		(%sp)+,&0x00fc		# restore d2-d7
361 	mov.l		%d6, -(%sp)
370 	sub.l		%d3, %d4		# U1U2 - V1q
380 #	add.l		%d6, %d4		# (U1U2 - V1q) + U3
383 	bls.b		lddadjd1		# is V2q > (U1U2-V1q) + U3 ?
389 	mov.l		%d5, -(%sp)		# save %d5 (%d6 already saved)
403 # - according to Knuth, this is done only 2 out of 65536 times for random
448 # factors for the 32X32->64 multiplication are in %d5 and %d6.
449 # returns 64 bit result in %d5 (hi) %d6(lo).
452 # multiply hi,lo words of each factor to get 4 intermediate products
458 	mulu.w		%d5, %d6		# %d6 <- lsw*lsw
459 	mulu.w		%d3, %d5		# %d5 <- msw-dest*lsw-source
460 	mulu.w		%d4, %d2		# %d2 <- msw-source*lsw-dest
461 	mulu.w		%d4, %d3		# %d3 <- msw*msw
480 #	_060LSP__imulu64_(): Emulate 64-bit unsigned mul instruction	#
481 #	_060LSP__imuls64_(): Emulate 64-bit signed mul instruction.	#
485 #	64-bit multiply instruction.					#
493 #	0xc(sp) = pointer to location to place 64-bit result		#
496 #	0xc(sp) = points to location of 64-bit result			#
499 #	Perform the multiply in pieces using 16x16->32 unsigned		#
506 set MUL64_CC, -4
512 	link.w		%a6,&-4
513 	movm.l		&0x3800,-(%sp)		# save d2-d4
514 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
527 #	----------------------------					#
528 #	| hi(mplier) * hi(mplicand)|					#
529 #	----------------------------					#
530 #		     -----------------------------			#
531 #		     | hi(mplier) * lo(mplicand) |			#
532 #		     -----------------------------			#
533 #		     -----------------------------			#
534 #		     | lo(mplier) * hi(mplicand) |			#
535 #		     -----------------------------			#
536 #	  |			   -----------------------------	#
537 #	--|--			   | lo(mplier) * lo(mplicand) |	#
538 #	  |			   -----------------------------	#
540 #	--------------------------------------------------------	#
541 #	|	hi(result)	   |	    lo(result)         |	#
542 #	--------------------------------------------------------	#
549 	swap		%d3			# hi(mr) in lo d3
550 	swap		%d4			# hi(md) in lo d4
554 	mulu.w		%d3,%d1			# [2] hi(mr) * lo(md)
555 	mulu.w		%d4,%d2			# [3] lo(mr) * hi(md)
556 	mulu.w		%d4,%d3			# [4] hi(mr) * hi(md)
558 # add lo portions of [2],[3] to hi portion of [1].
562 	swap		%d0			# hi([1]) <==> lo([1])
563 	add.w		%d1,%d0			# hi([1]) + lo([2])
565 	add.w		%d2,%d0			# hi([1]) + lo([3])
567 	swap		%d0			# lo([1]) <==> hi([1])
570 # now, clear lo, put hi in lo reg, and add to [4]
572 	clr.w		%d2			# clear hi([3])
573 	swap		%d1			# hi([2]) in lo d1
574 	swap		%d2			# hi([3]) in lo d2
575 	add.l		%d2,%d1			#    [4]  + hi([2])
576 	add.l		%d3,%d1			#    [4]  + hi([3])
597 	movm.l		(%sp)+,&0x001c		# restore d2-d4
604 # save the zero result to the register file and set the 'Z' ccode bit.
612 	mov.w		%d4,%cc			# set 'Z' ccode bit
623 	link.w		%a6,&-4
624 	movm.l		&0x3c00,-(%sp)		# save d2-d5
625 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
653 #	----------------------------					#
654 #	| hi(mplier) * hi(mplicand)|					#
655 #	----------------------------					#
656 #		     -----------------------------			#
657 #		     | hi(mplier) * lo(mplicand) |			#
658 #		     -----------------------------			#
659 #		     -----------------------------			#
660 #		     | lo(mplier) * hi(mplicand) |			#
661 #		     -----------------------------			#
662 #	  |			   -----------------------------	#
663 #	--|--			   | lo(mplier) * lo(mplicand) |	#
664 #	  |			   -----------------------------	#
666 #	--------------------------------------------------------	#
667 #	|	hi(result)	   |	    lo(result)         |	#
668 #	--------------------------------------------------------	#
675 	swap		%d3			# hi(mr) in lo d3
676 	swap		%d4			# hi(md) in lo d4
680 	mulu.w		%d3,%d1			# [2] hi(mr) * lo(md)
681 	mulu.w		%d4,%d2			# [3] lo(mr) * hi(md)
682 	mulu.w		%d4,%d3			# [4] hi(mr) * hi(md)
684 # add lo portions of [2],[3] to hi portion of [1].
688 	swap		%d0			# hi([1]) <==> lo([1])
689 	add.w		%d1,%d0			# hi([1]) + lo([2])
691 	add.w		%d2,%d0			# hi([1]) + lo([3])
693 	swap		%d0			# lo([1]) <==> hi([1])
696 # now, clear lo, put hi in lo reg, and add to [4]
698 	clr.w		%d2			# clear hi([3])
699 	swap		%d1			# hi([2]) in lo d1
700 	swap		%d2			# hi([3]) in lo d2
701 	add.l		%d2,%d1			#    [4]  + hi([2])
702 	add.l		%d3,%d1			#    [4]  + hi([3])
709 #   -negate all bits and add 1
712 	not.l		%d1			# negate hi(result) bits
714 	addx.l		%d4,%d1			# add carry to hi(result)
734 	movm.l		(%sp)+,&0x003c		# restore d2-d5
741 # save the zero result to the register file and set the 'Z' ccode bit.
749 	mov.w		%d4,%cc			# set 'Z' ccode bit
786 set	CMP2_CC,	-4
792 	link.w		%a6,&-4
793 	movm.l		&0x3800,-(%sp)		# save d2-d4
794 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
804 	extb.l		%d1			# sign extend hi bnd
811 	link.w		%a6,&-4
812 	movm.l		&0x3800,-(%sp)		# save d2-d4
813 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
823 	ext.l		%d1			# sign extend hi bnd
830 	link.w		%a6,&-4
831 	movm.l		&0x3800,-(%sp)		# save d2-d4
832 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
846 	link.w		%a6,&-4
847 	movm.l		&0x3800,-(%sp)		# save d2-d4
848 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
858 	extb.l		%d1			# sign extend hi bnd
869 	link.w		%a6,&-4
870 	movm.l		&0x3800,-(%sp)		# save d2-d4
871 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
881 	ext.l		%d1			# sign extend hi bnd
892 	link.w		%a6,&-4
893 	movm.l		&0x3800,-(%sp)		# save d2-d4
894 #	fmovm.l		&0x0,-(%sp)		# save no fpregs
905 #	(1) save 'Z' bit from (Rn - lo)
906 #	(2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
911 	sub.l		%d0, %d2		# (Rn - lo)
913 	andi.b		&0x4, %d3		# keep 'Z' bit
914 	sub.l		%d0, %d1		# (hi - lo)
915 	cmp.l		%d1,%d2			# ((hi - lo) - (Rn - hi))
919 	andi.b		&0x5, %d3		# keep 'Z' and 'N'
928 	movm.l		(%sp)+,&0x001c		# restore d2-d4