m68k/coldfire/m5441x.c

21 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
22 DEFINE_CLK(0, "flexcan.0", 8, MCF_CLK);
23 DEFINE_CLK(0, "flexcan.1", 9, MCF_CLK);
24 DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
25 DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
26 DEFINE_CLK(0, "edma", 17, MCF_CLK);
27 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
28 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
29 DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
30 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
31 DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
36 DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
37 DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
38 DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
39 DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
40 DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
41 DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
42 DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
43 DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
44 DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
45 DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
46 DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
47 DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
48 DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
49 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
50 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
51 DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
52 DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
53 DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
54 DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
55 DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
56 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
57 DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
58 DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
59 DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
60 DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
61 DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
63 DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
64 DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK);
65 DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK);
66 DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK);
67 DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK);
78 DEFINE_CLK(2, "ipg.0", 0, MCF_CLK);
79 DEFINE_CLK(2, "ahb.0", 1, MCF_CLK);
80 DEFINE_CLK(2, "per.0", 2, MCF_CLK);