m68k/coldfire/m53xx.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
5  *	m53xx.c -- platform support for ColdFire 53xx based boards
7  *	Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
56 DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
59 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
60 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
77 	CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
94 	CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
97 	CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
98 	CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
121 	&__clk_0_41,	/* gpio.0 */
130 	&__clk_0_22,	/* imx1-i2c.0 */
140 	&__clk_0_44,	/* mcfusb-otg.0 */
141 	&__clk_0_45,	/* mcfusb-host.0 */
168 	/* setup QSPS pins for QSPI with gpio CS control */  in m53xx_qspi_init()
190 	/* UART GPIO initialization */  in m53xx_uarts_init()
200 	/* Set multi-function pins to ethernet mode for fec0 */  in m53xx_fec_init()
220 		commandp[size-1] = 0;  in config_BSP()
337 	/* Latch chip select */  in fbcs_init()
343 	/* Initialize latch to drive signals to inactive states */  in fbcs_init()
393 		MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |  in sdramc_init()
394 		MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),  in sdramc_init()
405 		MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |  in sdramc_init()
462 	 * Initialize TIN3 as a GPIO output to enable the write  in gpio_init()
463 	 * half of the latch.  in gpio_init()
535 	/* Errata - workaround for SDRAM operation after exiting LIMP mode */  in clock_pll()