48 	unsigned int imm, imm_l, imm_h, rd, rj;  in simu_branch()  local
70 	rj = insn.reg1i21_format.rj;  in simu_branch()
73 		if (regs->regs[rj] == 0)  in simu_branch()
79 		if (regs->regs[rj] != 0)  in simu_branch()
87 	rj = insn.reg2i16_format.rj;  in simu_branch()
91 		if (regs->regs[rj] == regs->regs[rd])  in simu_branch()
97 		if (regs->regs[rj] != regs->regs[rd])  in simu_branch()
103 		if ((long)regs->regs[rj] < (long)regs->regs[rd])  in simu_branch()
109 		if ((long)regs->regs[rj] >= (long)regs->regs[rd])  in simu_branch()
115 		if (regs->regs[rj] < regs->regs[rd])  in simu_branch()
121 		if (regs->regs[rj] >= regs->regs[rd])  in simu_branch()
127 		regs->csr_era = regs->regs[rj] + sign_extend64(imm << 2, 17);  in simu_branch()
270 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk)  in larch_insn_gen_or()  argument
274 	emit_or(&insn, rd, rj, rk);  in larch_insn_gen_or()
279 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj)  in larch_insn_gen_move()  argument
281 	return larch_insn_gen_or(rd, rj, 0);  in larch_insn_gen_move()
312 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)  in larch_insn_gen_lu52id()  argument
321 	emit_lu52id(&insn, rd, rj, imm);  in larch_insn_gen_lu52id()
326 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)  in larch_insn_gen_jirl()  argument
335 	emit_jirl(&insn, rj, rd, imm >> 2);  in larch_insn_gen_jirl()