Lines Matching +full:0 +full:x03400000
13 #define INSN_NOP 0x03400000
14 #define INSN_BREAK 0x002a0000
15 #define INSN_HVCL 0x002b8000
17 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
18 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
19 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000
20 #define ADDR_IMMMASK_ORI 0x0000000000000FFF
21 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
29 #define ADDR_IMMSHIFT_ORI 0
38 break_op = 0x54,
42 b_op = 0x14,
43 bl_op = 0x15,
47 lu12iw_op = 0x0a,
48 lu32id_op = 0x0b,
49 pcaddi_op = 0x0c,
50 pcalau12i_op = 0x0d,
51 pcaddu12i_op = 0x0e,
52 pcaddu18i_op = 0x0f,
56 beqz_op = 0x10,
57 bnez_op = 0x11,
58 bceqz_op = 0x12, /* bits[9:8] = 0x00 */
59 bcnez_op = 0x12, /* bits[9:8] = 0x01 */
63 revb2h_op = 0x0c,
64 revb4h_op = 0x0d,
65 revb2w_op = 0x0e,
66 revbd_op = 0x0f,
67 revh2w_op = 0x10,
68 revhd_op = 0x11,
69 extwh_op = 0x16,
70 extwb_op = 0x17,
71 cpucfg_op = 0x1b,
72 iocsrrdb_op = 0x19200,
73 iocsrrdh_op = 0x19201,
74 iocsrrdw_op = 0x19202,
75 iocsrrdd_op = 0x19203,
76 iocsrwrb_op = 0x19204,
77 iocsrwrh_op = 0x19205,
78 iocsrwrw_op = 0x19206,
79 iocsrwrd_op = 0x19207,
83 slliw_op = 0x81,
84 srliw_op = 0x89,
85 sraiw_op = 0x91,
89 sllid_op = 0x41,
90 srlid_op = 0x45,
91 sraid_op = 0x49,
95 addiw_op = 0x0a,
96 addid_op = 0x0b,
97 lu52id_op = 0x0c,
98 andi_op = 0x0d,
99 ori_op = 0x0e,
100 xori_op = 0x0f,
101 ldb_op = 0xa0,
102 ldh_op = 0xa1,
103 ldw_op = 0xa2,
104 ldd_op = 0xa3,
105 stb_op = 0xa4,
106 sth_op = 0xa5,
107 stw_op = 0xa6,
108 std_op = 0xa7,
109 ldbu_op = 0xa8,
110 ldhu_op = 0xa9,
111 ldwu_op = 0xaa,
112 flds_op = 0xac,
113 fsts_op = 0xad,
114 fldd_op = 0xae,
115 fstd_op = 0xaf,
119 llw_op = 0x20,
120 scw_op = 0x21,
121 lld_op = 0x22,
122 scd_op = 0x23,
123 ldptrw_op = 0x24,
124 stptrw_op = 0x25,
125 ldptrd_op = 0x26,
126 stptrd_op = 0x27,
130 jirl_op = 0x13,
131 beq_op = 0x16,
132 bne_op = 0x17,
133 blt_op = 0x18,
134 bge_op = 0x19,
135 bltu_op = 0x1a,
136 bgeu_op = 0x1b,
140 bstrinsd_op = 0x2,
141 bstrpickd_op = 0x3,
145 asrtle_op = 0x02,
146 asrtgt_op = 0x03,
147 addw_op = 0x20,
148 addd_op = 0x21,
149 subw_op = 0x22,
150 subd_op = 0x23,
151 nor_op = 0x28,
152 and_op = 0x29,
153 or_op = 0x2a,
154 xor_op = 0x2b,
155 orn_op = 0x2c,
156 andn_op = 0x2d,
157 sllw_op = 0x2e,
158 srlw_op = 0x2f,
159 sraw_op = 0x30,
160 slld_op = 0x31,
161 srld_op = 0x32,
162 srad_op = 0x33,
163 mulw_op = 0x38,
164 mulhw_op = 0x39,
165 mulhwu_op = 0x3a,
166 muld_op = 0x3b,
167 mulhd_op = 0x3c,
168 mulhdu_op = 0x3d,
169 divw_op = 0x40,
170 modw_op = 0x41,
171 divwu_op = 0x42,
172 modwu_op = 0x43,
173 divd_op = 0x44,
174 modd_op = 0x45,
175 divdu_op = 0x46,
176 moddu_op = 0x47,
177 ldxb_op = 0x7000,
178 ldxh_op = 0x7008,
179 ldxw_op = 0x7010,
180 ldxd_op = 0x7018,
181 stxb_op = 0x7020,
182 stxh_op = 0x7028,
183 stxw_op = 0x7030,
184 stxd_op = 0x7038,
185 ldxbu_op = 0x7040,
186 ldxhu_op = 0x7048,
187 ldxwu_op = 0x7050,
188 fldxs_op = 0x7060,
189 fldxd_op = 0x7068,
190 fstxs_op = 0x7070,
191 fstxd_op = 0x7078,
192 amswapw_op = 0x70c0,
193 amswapd_op = 0x70c1,
194 amaddw_op = 0x70c2,
195 amaddd_op = 0x70c3,
196 amandw_op = 0x70c4,
197 amandd_op = 0x70c5,
198 amorw_op = 0x70c6,
199 amord_op = 0x70c7,
200 amxorw_op = 0x70c8,
201 amxord_op = 0x70c9,
202 ammaxw_op = 0x70ca,
203 ammaxd_op = 0x70cb,
204 amminw_op = 0x70cc,
205 ammind_op = 0x70cd,
206 ammaxwu_op = 0x70ce,
207 ammaxdu_op = 0x70cf,
208 amminwu_op = 0x70d0,
209 ammindu_op = 0x70d1,
210 amswapdbw_op = 0x70d2,
211 amswapdbd_op = 0x70d3,
212 amadddbw_op = 0x70d4,
213 amadddbd_op = 0x70d5,
214 amanddbw_op = 0x70d6,
215 amanddbd_op = 0x70d7,
216 amordbw_op = 0x70d8,
217 amordbd_op = 0x70d9,
218 amxordbw_op = 0x70da,
219 amxordbd_op = 0x70db,
220 ammaxdbw_op = 0x70dc,
221 ammaxdbd_op = 0x70dd,
222 ammindbw_op = 0x70de,
223 ammindbd_op = 0x70df,
224 ammaxdbwu_op = 0x70e0,
225 ammaxdbdu_op = 0x70e1,
226 ammindbwu_op = 0x70e2,
227 ammindbdu_op = 0x70e3,
228 fldgts_op = 0x70e8,
229 fldgtd_op = 0x70e9,
230 fldles_op = 0x70ea,
231 fldled_op = 0x70eb,
232 fstgts_op = 0x70ec,
233 fstgtd_op = 0x70ed,
234 fstles_op = 0x70ee,
235 fstled_op = 0x70ef,
236 ldgtb_op = 0x70f0,
237 ldgth_op = 0x70f1,
238 ldgtw_op = 0x70f2,
239 ldgtd_op = 0x70f3,
240 ldleb_op = 0x70f4,
241 ldleh_op = 0x70f5,
242 ldlew_op = 0x70f6,
243 ldled_op = 0x70f7,
244 stgtb_op = 0x70f8,
245 stgth_op = 0x70f9,
246 stgtw_op = 0x70fa,
247 stgtd_op = 0x70fb,
248 stleb_op = 0x70fc,
249 stleh_op = 0x70fd,
250 stlew_op = 0x70fe,
251 stled_op = 0x70ff,
255 alslw_op = 0x02,
256 alslwu_op = 0x03,
257 alsld_op = 0x16,
376 LOONGARCH_GPR_ZERO = 0,
457 if (ip->reg0i26_format.immediate_l == 0
458 && ip->reg0i26_format.immediate_h == 0)
466 if (ip->reg1i21_format.immediate_l == 0
467 && ip->reg1i21_format.immediate_h == 0)
478 if (ip->reg2i16_format.immediate == 0)
544 immediate_l = offset & 0xffff; \
546 immediate_h = offset & 0x3ff; \