Lines Matching full:r0
37 memd(R0 + #_PT_R3130) = R31:30; \
38 { memw(R0 + #_PT_R2928) = R28; \
39 R31 = memw(R0 + #_PT_ER_VMPSP); }\
40 { memw(R0 + #(_PT_R2928 + 4)) = R31; \
42 { memd(R0 + #_PT_R2726) = R27:26; \
44 memd(R0 + #_PT_R2524) = R25:24; \
45 memd(R0 + #_PT_R2322) = R23:22; \
46 memd(R0 + #_PT_R2120) = R21:20; \
47 memd(R0 + #_PT_R1918) = R19:18; \
48 memd(R0 + #_PT_R1716) = R17:16; \
49 memd(R0 + #_PT_R1514) = R15:14; \
50 memd(R0 + #_PT_R1312) = R13:12; \
51 { memd(R0 + #_PT_R1110) = R11:10; \
53 { memd(R0 + #_PT_R0908) = R9:8; \
55 { memd(R0 + #_PT_R0706) = R7:6; \
57 { memd(R0 + #_PT_R0504) = R5:4; \
59 { memd(R0 + #_PT_GPUGP) = R31:30; \
62 { memd(R0 + #_PT_LC0SA0) = R15:14; \
65 { memd(R0 + #_PT_LC1SA1) = R13:12; \
68 { memd(R0 + #_PT_M1M0) = R11:10; \
70 R2 = and(R0,R2); } \
71 { memd(R0 + #_PT_PREDSUSR) = R15:14; \
74 memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
76 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
82 { memd(R0 + #_PT_R3130) = R31:30; \
83 R30 = memw(R0 + #_PT_ER_VMPSP); }\
84 { memw(R0 + #_PT_R2928) = R28; \
85 memw(R0 + #(_PT_R2928 + 4)) = R30; }\
87 memd(R0 + #_PT_R2726) = R27:26; \
88 memd(R0 + #_PT_R2524) = R25:24; }\
89 { memd(R0 + #_PT_R2322) = R23:22; \
90 memd(R0 + #_PT_R2120) = R21:20; }\
91 { memd(R0 + #_PT_R1918) = R19:18; \
92 memd(R0 + #_PT_R1716) = R17:16; }\
93 { memd(R0 + #_PT_R1514) = R15:14; \
94 memd(R0 + #_PT_R1312) = R13:12; \
96 { memd(R0 + #_PT_R1110) = R11:10; \
97 memd(R0 + #_PT_R0908) = R9:8; \
99 { memd(R0 + #_PT_R0706) = R7:6; \
100 memd(R0 + #_PT_R0504) = R5:4; \
102 { memd(R0 + #_PT_GPUGP) = R31:30; \
103 memd(R0 + #_PT_LC0SA0) = R15:14; \
105 { THREADINFO_REG = and(R0, # ## #-_THREAD_SIZE); \
106 memd(R0 + #_PT_LC1SA1) = R13:12; \
108 { memd(R0 + #_PT_M1M0) = R11:10; \
109 memw(R0 + #_PT_PREDSUSR + 4) = R15; }\
111 memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
113 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
114 memd(R0 + #_PT_CS1CS0) = R17:16; \
127 R15:14 = memd(R0 + #_PT_PREDSUSR); } \
128 { R11:10 = memd(R0 + #_PT_M1M0); \
130 { R13:12 = memd(R0 + #_PT_LC1SA1); \
132 { R15:14 = memd(R0 + #_PT_LC0SA0); \
134 { R3:2 = memd(R0 + #_PT_R0302); \
136 { R5:4 = memd(R0 + #_PT_R0504); \
138 { R7:6 = memd(R0 + #_PT_R0706); \
140 { R9:8 = memd(R0 + #_PT_R0908); \
142 { R11:10 = memd(R0 + #_PT_R1110); \
144 { R13:12 = memd(R0 + #_PT_R1312); \
145 R15:14 = memd(R0 + #_PT_R1514); } \
146 { R17:16 = memd(R0 + #_PT_R1716); \
147 R19:18 = memd(R0 + #_PT_R1918); } \
148 { R21:20 = memd(R0 + #_PT_R2120); \
149 R23:22 = memd(R0 + #_PT_R2322); } \
150 { R25:24 = memd(R0 + #_PT_R2524); \
151 R27:26 = memd(R0 + #_PT_R2726); } \
152 R31:30 = memd(R0 + #_PT_GPUGP); \
153 { R28 = memw(R0 + #_PT_R2928); \
155 { R31:30 = memd(R0 + #_PT_R3130); \
161 R15:14 = memd(R0 + #_PT_PREDSUSR); } \
162 { R11:10 = memd(R0 + #_PT_M1M0); \
163 R13:12 = memd(R0 + #_PT_LC1SA1); \
165 { R15:14 = memd(R0 + #_PT_LC0SA0); \
166 R3:2 = memd(R0 + #_PT_R0302); \
168 { R5:4 = memd(R0 + #_PT_R0504); \
169 R7:6 = memd(R0 + #_PT_R0706); \
171 { R9:8 = memd(R0 + #_PT_R0908); \
172 R11:10 = memd(R0 + #_PT_R1110); \
174 { R13:12 = memd(R0 + #_PT_R1312); \
175 R15:14 = memd(R0 + #_PT_R1514); \
177 { R17:16 = memd(R0 + #_PT_R1716); \
178 R19:18 = memd(R0 + #_PT_R1918); } \
179 { R21:20 = memd(R0 + #_PT_R2120); \
180 R23:22 = memd(R0 + #_PT_R2322); } \
181 { R25:24 = memd(R0 + #_PT_R2524); \
182 R27:26 = memd(R0 + #_PT_R2726); } \
183 R31:30 = memd(R0 + #_PT_CS1CS0); \
185 R31:30 = memd(R0 + #_PT_GPUGP) ; \
186 R28 = memw(R0 + #_PT_R2928); }\
188 R31:30 = memd(R0 + #_PT_R3130); }
193 * of pt_regs in HVM mode. Save R0/R1, set handler's address in R1.
194 * R0 is the address of pt_regs and is the parameter to save_pt_regs.
200 * Need to save off R0, R1, R2, R3 immediately.
215 R0 = R29; \
232 R0 = usr; \
235 memw(R29 + #_PT_PREDSUSR) = R0; \
236 R0 = setbit(R0, #16); \
238 usr = R0; \
246 R0 = R29; \
274 R0 = #VM_INT_DISABLE define
280 R0 = memw(R29 + #_PT_ER_VMEST); define
284 P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
287 R0 = #VM_INT_DISABLE; define
294 * R26 needs to have do_work_pending, and R0 should have VM_INT_DISABLE
301 R0 = R29; /* regs should still be at top of stack */ define
307 P0 = cmp.eq(R0, #0); if (!P0.new) jump:nt check_work_pending;
308 R0 = #VM_INT_DISABLE; define
314 * R0 gets preloaded with #VM_INT_DISABLE before we get here.
331 R0 = R29 define
370 R0 = #VM_INT_DISABLE; define
374 R0 = R25; define
379 R0 = #VM_INT_DISABLE; define