Lines Matching full:res1
122 res1 = "UL(0)"
135 define(reg "_RES1", "(" res1 ")")
141 res1 = null
161 res1 = "UL(0)"
186 if (res1 != null)
187 define(reg "_RES1", "(" res1 ")")
190 if (res0 != null || res1 != null || unkn != null)
200 res1 = null
220 res1 = null
237 /^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
239 parse_bitdef(reg, "RES1", $2)
242 res1 = res1 " | GENMASK_ULL(" msb ", " lsb ")"