arm64/lib/copy_template.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
9  * http://bazaar.launchpad.net/~linaro-toolchain-dev/cortex-strings/trunk/
18  *	x0 - dest
19  *	x1 - src
20  *	x2 - n
22  *	x0 - dest
43 	cmp	count, #16
44 	/*When memory length is less than 16, the accessed are not aligned.*/
55 	* dst is less than 16. The memory accesses here are alignment.
57 	tbz	tmp2, #0, 1f
58 	ldrb1	tmp1w, src, #1
59 	strb1	tmp1w, dst, #1
60 1:
61 	tbz	tmp2, #1, 2f
88 	b.eq	1f
90 	ldp1	A_l, A_h, src, #16
91 	stp1	A_l, A_h, dst, #16
92 1:
93 	ldp1	A_l, A_h, src, #16
94 	stp1	A_l, A_h, dst, #16
96 	ldp1	A_l, A_h, src, #16
97 	stp1	A_l, A_h, dst, #16
101 	* memory in an increasing address order,rather than to load/store 16
102 	* bytes from (src-16) to (dst-16) and to backward the src to aligned
105 	* precondition that src address is at least 16 bytes bigger than dst
110 	tbz	count, #3, 1f
113 1:
118 	tbz	count, #1, 3f
123 	ldrb1	tmp1w, src, #1
124 	strb1	tmp1w, dst, #1
135 	ldp1	A_l, A_h, src, #16
136 	stp1	A_l, A_h, dst, #16
137 	ldp1	B_l, B_h, src, #16
138 	ldp1	C_l, C_h, src, #16
139 	stp1	B_l, B_h, dst, #16
140 	stp1	C_l, C_h, dst, #16
141 	ldp1	D_l, D_h, src, #16
142 	stp1	D_l, D_h, dst, #16
154 	/* pre-get 64 bytes data. */
155 	ldp1	A_l, A_h, src, #16
156 	ldp1	B_l, B_h, src, #16
157 	ldp1	C_l, C_h, src, #16
158 	ldp1	D_l, D_h, src, #16
159 1:
164 	stp1	A_l, A_h, dst, #16
165 	ldp1	A_l, A_h, src, #16
166 	stp1	B_l, B_h, dst, #16
167 	ldp1	B_l, B_h, src, #16
168 	stp1	C_l, C_h, dst, #16
169 	ldp1	C_l, C_h, src, #16
170 	stp1	D_l, D_h, dst, #16
171 	ldp1	D_l, D_h, src, #16
173 	b.ge	1b
174 	stp1	A_l, A_h, dst, #16
175 	stp1	B_l, B_h, dst, #16
176 	stp1	C_l, C_h, dst, #16
177 	stp1	D_l, D_h, dst, #16