Lines Matching refs:undef_access
51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, in undef_access() function
65 return undef_access(vcpu, params, r); in bad_trap()
357 return undef_access(vcpu, p, r); in access_dcgsw()
395 return undef_access(vcpu, p, r); in access_vm_reg()
443 return undef_access(vcpu, p, r); in access_gic_sgi()
489 return undef_access(vcpu, p, r); in access_gic_sre()
521 return undef_access(vcpu, p, r); in trap_loregion()
1255 return undef_access(vcpu, p, r); in access_pmuserenr()
1340 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1341 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1342 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1343 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1358 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1397 return undef_access(vcpu, p, r); in access_arch_timer()
2057 .access = undef_access, \
2328 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
2486 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
2487 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2488 { SYS_DESC(SYS_SMCR_EL1), undef_access },
2503 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
2524 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2525 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2526 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2527 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2528 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2529 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2530 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2531 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2532 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2533 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2534 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2561 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
2562 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
2563 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
2564 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
2565 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
2566 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
2567 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
2568 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
2569 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
2570 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
2571 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
2572 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
2573 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
2574 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
2578 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
2579 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
2580 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
2581 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
2582 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
2584 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
2585 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
2590 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2592 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2599 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2600 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
2606 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
2607 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
2654 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2656 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2658 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2659 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2660 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2661 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2662 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2663 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2664 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2665 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2832 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },
2846 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },
2850 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
2860 { SYS_DESC(SYS_RMR_EL2), undef_access },
2934 return undef_access(vcpu, p, r); in handle_alle1is()
3027 return undef_access(vcpu, p, r); in handle_vmalls12e1is()
3053 return undef_access(vcpu, p, r); in handle_ripas2e1is()
3126 return undef_access(vcpu, p, r); in handle_ipas2e1is()
3167 return undef_access(vcpu, p, r); in handle_tlbi_el1()
3291 SYS_INSN(TLBI_ALLE2OS, undef_access),
3292 SYS_INSN(TLBI_VAE2OS, undef_access),
3294 SYS_INSN(TLBI_VALE2OS, undef_access),
3297 SYS_INSN(TLBI_RVAE2IS, undef_access),
3298 SYS_INSN(TLBI_RVALE2IS, undef_access),
3310 SYS_INSN(TLBI_RVAE2OS, undef_access),
3311 SYS_INSN(TLBI_RVALE2OS, undef_access),
3312 SYS_INSN(TLBI_RVAE2, undef_access),
3313 SYS_INSN(TLBI_RVALE2, undef_access),
3322 SYS_INSN(TLBI_ALLE2OSNXS, undef_access),
3323 SYS_INSN(TLBI_VAE2OSNXS, undef_access),
3325 SYS_INSN(TLBI_VALE2OSNXS, undef_access),
3328 SYS_INSN(TLBI_RVAE2ISNXS, undef_access),
3329 SYS_INSN(TLBI_RVALE2ISNXS, undef_access),
3330 SYS_INSN(TLBI_ALLE2ISNXS, undef_access),
3331 SYS_INSN(TLBI_VAE2ISNXS, undef_access),
3334 SYS_INSN(TLBI_VALE2ISNXS, undef_access),
3344 SYS_INSN(TLBI_RVAE2OSNXS, undef_access),
3345 SYS_INSN(TLBI_RVALE2OSNXS, undef_access),
3346 SYS_INSN(TLBI_RVAE2NXS, undef_access),
3347 SYS_INSN(TLBI_RVALE2NXS, undef_access),
3348 SYS_INSN(TLBI_ALLE2NXS, undef_access),
3349 SYS_INSN(TLBI_VAE2NXS, undef_access),
3351 SYS_INSN(TLBI_VALE2NXS, undef_access),
3529 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
3579 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
3580 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
3581 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
3582 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
3583 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
3584 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
3585 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
3586 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
3587 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
3588 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
3589 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
3590 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
3591 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
3592 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
3593 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
3594 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
3595 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
3596 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
3597 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
3599 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
3600 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
3679 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },