120 	counter = __vcpu_sys_reg(vcpu, reg);  in kvm_pmu_get_pmc_value()
166 		val  = __vcpu_sys_reg(vcpu, reg) & GENMASK(63, 32);  in kvm_pmu_set_pmc_value()
170 	__vcpu_sys_reg(vcpu, reg) = val;  in kvm_pmu_set_pmc_value()
221 	__vcpu_sys_reg(vcpu, reg) = val;  in kvm_pmu_stop_counter()
344 		reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);  in kvm_pmu_overflow_status()
345 		reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);  in kvm_pmu_overflow_status()
346 		reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);  in kvm_pmu_overflow_status()
449 	mask &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);  in kvm_pmu_counter_increment()
456 		type = __vcpu_sys_reg(vcpu, counter_index_to_evtreg(i));  in kvm_pmu_counter_increment()
462 		reg = __vcpu_sys_reg(vcpu, counter_index_to_reg(i)) + 1;  in kvm_pmu_counter_increment()
465 		__vcpu_sys_reg(vcpu, counter_index_to_reg(i)) = reg;  in kvm_pmu_counter_increment()
472 		__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);  in kvm_pmu_counter_increment()
518 	__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx);  in kvm_pmu_perf_overflow()
563 	__vcpu_sys_reg(vcpu, PMCR_EL0) = val & ~(ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_P);  in kvm_pmu_handle_pmcr()
567 		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));  in kvm_pmu_handle_pmcr()
570 		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));  in kvm_pmu_handle_pmcr()
589 	       (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(pmc->idx));  in kvm_pmu_counter_is_enabled()
606 	data = __vcpu_sys_reg(vcpu, reg);  in kvm_pmu_create_perf_event()
688 	__vcpu_sys_reg(vcpu, reg) = data & kvm_pmu_evtyper_mask(vcpu->kvm);  in kvm_pmu_set_counter_event_type()
811 	__vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= mask;  in kvm_vcpu_reload_pmu()
812 	__vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= mask;  in kvm_vcpu_reload_pmu()
813 	__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= mask;  in kvm_vcpu_reload_pmu()
1138 	u64 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);  in kvm_vcpu_read_pmcr()