947 		v |= masks->mask[sr].res1;  in kvm_vcpu_sanitise_vncr_reg()
953 static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1)  in set_sysreg_masks()  argument
958 	kvm->arch.sysreg_masks->mask[i].res1 = res1;  in set_sysreg_masks()
963 	u64 res0, res1;  in kvm_init_nv_sysregs()  local
978 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
983 	set_sysreg_masks(kvm, VTTBR_EL2, res0, res1);  in kvm_init_nv_sysregs()
987 	res1 = BIT(31);  in kvm_init_nv_sysregs()
988 	set_sysreg_masks(kvm, VTCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
992 	res1 = BIT(31);  in kvm_init_nv_sysregs()
993 	set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1);  in kvm_init_nv_sysregs()
997 	res1 = HCR_RW;  in kvm_init_nv_sysregs()
1029 		res1 |= HCR_E2H;  in kvm_init_nv_sysregs()
1030 	set_sysreg_masks(kvm, HCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1034 	res1 = HCRX_EL2_RES1;  in kvm_init_nv_sysregs()
1072 	set_sysreg_masks(kvm, HCRX_EL2, res0, res1);  in kvm_init_nv_sysregs()
1075 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
1112 	set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1113 	set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1116 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
1151 	set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1160 	set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1164 	res1 = HFGITR_EL2_RES1;  in kvm_init_nv_sysregs()
1194 	set_sysreg_masks(kvm, HFGITR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1198 	res1 = HAFGRTR_EL2_RES1;  in kvm_init_nv_sysregs()
1200 		res0 |= ~(res0 | res1);  in kvm_init_nv_sysregs()
1201 	set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1205 	res1 = SCTLR_EL1_RES1;  in kvm_init_nv_sysregs()
1208 	set_sysreg_masks(kvm, SCTLR_EL1, res0, res1);  in kvm_init_nv_sysregs()