50 static void fail_s1_walk(struct s1_walk_result *wr, u8 fst, bool ptw, bool s2)  in fail_s1_walk()  argument
52 	wr->fst		= fst;  in fail_s1_walk()
53 	wr->ptw		= ptw;  in fail_s1_walk()
54 	wr->s2		= s2;  in fail_s1_walk()
55 	wr->failed	= true;  in fail_s1_walk()
91 			 struct s1_walk_result *wr, u64 va)  in setup_s1_walk()  argument
156 			wr->level = S1_MMU_DISABLED;  in setup_s1_walk()
163 			wr->level = S1_MMU_DISABLED;  in setup_s1_walk()
167 	if (wr->level == S1_MMU_DISABLED) {  in setup_s1_walk()
171 		wr->pa = va;  in setup_s1_walk()
280 	fail_s1_walk(wr, ESR_ELx_FSC_ADDRSZ_L(0), false, false);  in setup_s1_walk()
284 	fail_s1_walk(wr, ESR_ELx_FSC_FAULT_L(0), false, false);  in setup_s1_walk()
289 		   struct s1_walk_result *wr, u64 va)  in walk_s1()  argument
313 				fail_s1_walk(wr,  in walk_s1()
320 				fail_s1_walk(wr, ESR_ELx_FSC_PERM_L(level),  in walk_s1()
331 			fail_s1_walk(wr, ESR_ELx_FSC_SEA_TTW(level),  in walk_s1()
355 			wr->APTable  |= FIELD_GET(S1_TABLE_AP, desc);  in walk_s1()
356 			wr->UXNTable |= FIELD_GET(PMD_TABLE_UXN, desc);  in walk_s1()
357 			wr->PXNTable |= FIELD_GET(PMD_TABLE_PXN, desc);  in walk_s1()
394 	wr->failed = false;  in walk_s1()
395 	wr->level = level;  in walk_s1()
396 	wr->desc = desc;  in walk_s1()
397 	wr->pa = desc & GENMASK(47, va_bottom);  in walk_s1()
398 	wr->pa |= va & GENMASK_ULL(va_bottom - 1, 0);  in walk_s1()
403 	fail_s1_walk(wr, ESR_ELx_FSC_ADDRSZ_L(level), true, false);  in walk_s1()
406 	fail_s1_walk(wr, ESR_ELx_FSC_FAULT_L(level), true, false);  in walk_s1()
679 static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr,  in compute_par_s1()  argument
684 	if (wr->failed) {  in compute_par_s1()
687 		par |= FIELD_PREP(SYS_PAR_EL1_FST, wr->fst);  in compute_par_s1()
688 		par |= wr->ptw ? SYS_PAR_EL1_PTW : 0;  in compute_par_s1()
689 		par |= wr->s2 ? SYS_PAR_EL1_S : 0;  in compute_par_s1()
690 	} else if (wr->level == S1_MMU_DISABLED) {  in compute_par_s1()
693 		par |= wr->pa & GENMASK_ULL(47, 12);  in compute_par_s1()
714 		mair >>= FIELD_GET(PTE_ATTRINDX_MASK, wr->desc) * 8;  in compute_par_s1()
726 		par |= wr->pa & GENMASK_ULL(47, 12);  in compute_par_s1()
728 		sh = compute_sh(mair, wr->desc);  in compute_par_s1()
753 	struct s1_walk_result wr = {};  in handle_at_slow()  local
757 	ret = setup_s1_walk(vcpu, op, &wi, &wr, vaddr);  in handle_at_slow()
761 	if (wr.level == S1_MMU_DISABLED)  in handle_at_slow()
766 	ret = walk_s1(vcpu, &wi, &wr, vaddr);  in handle_at_slow()
776 		switch (FIELD_GET(PTE_USER | PTE_RDONLY, wr.desc)) {  in handle_at_slow()
794 		switch (wr.APTable) {  in handle_at_slow()
809 		px = !((wr.desc & PTE_PXN) || wr.PXNTable || uw);  in handle_at_slow()
810 		ux = !((wr.desc & PTE_UXN) || wr.UXNTable);  in handle_at_slow()
823 		if (!(wr.desc & PTE_RDONLY)) {  in handle_at_slow()
830 		if (wr.APTable & BIT(1))  in handle_at_slow()
834 		px = !((wr.desc & PTE_UXN) || wr.UXNTable);  in handle_at_slow()
864 		fail_s1_walk(&wr, ESR_ELx_FSC_PERM_L(wr.level), false, false);  in handle_at_slow()
867 	return compute_par_s1(vcpu, &wr, wi.regime);  in handle_at_slow()