Lines Matching full:xn
54 int xn = opcode & 0x1f; in check_cbz() local
57 (get_x_reg(regs, xn) == 0) : (get_w_reg(regs, xn) == 0); in check_cbz()
62 int xn = opcode & 0x1f; in check_cbnz() local
65 (get_x_reg(regs, xn) != 0) : (get_w_reg(regs, xn) != 0); in check_cbnz()
70 int xn = opcode & 0x1f; in check_tbz() local
73 return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) == 0; in check_tbz()
78 int xn = opcode & 0x1f; in check_tbnz() local
81 return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) != 0; in check_tbnz()
90 long imm, xn, val; in simulate_adr_adrp() local
92 xn = opcode & 0x1f; in simulate_adr_adrp()
100 set_x_reg(regs, xn, val); in simulate_adr_adrp()
131 int xn = (opcode >> 5) & 0x1f; in simulate_br_blr_ret() local
134 instruction_pointer_set(regs, get_x_reg(regs, xn)); in simulate_br_blr_ret()
175 int xn = opcode & 0x1f; in simulate_ldr_literal() local
180 set_x_reg(regs, xn, READ_ONCE(*(u64 *)load_addr)); in simulate_ldr_literal()
182 set_w_reg(regs, xn, READ_ONCE(*(u32 *)load_addr)); in simulate_ldr_literal()
191 int xn = opcode & 0x1f; in simulate_ldrsw_literal() local
195 set_x_reg(regs, xn, READ_ONCE(*(s32 *)load_addr)); in simulate_ldrsw_literal()