Lines Matching +full:5 +full:- +full:8
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
34 #define CRm_shift 8
36 #define Op2_shift 5
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
112 /* Register-based PAN access, for save/restore purposes */
131 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
132 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
136 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
140 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
146 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
150 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
154 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
167 #include "asm/sysreg-defs.h"
178 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
191 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
196 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
200 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
202 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
204 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
230 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
237 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
279 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
283 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
308 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
309 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
310 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
312 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
313 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
314 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
315 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
316 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
317 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
318 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
319 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
320 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
321 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
322 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
323 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
324 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
325 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
326 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
333 #define SYS_PAR_EL1_PTW BIT(8)
343 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
353 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
371 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
385 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
386 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
387 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
388 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
389 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
401 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
409 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
413 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
437 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
448 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
457 * n: 0-15
463 * n: 0-15
480 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
494 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
505 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
532 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
533 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
534 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
535 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
536 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
537 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
538 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
547 #define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0)
554 #define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5)
562 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
575 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
580 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
589 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
599 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
624 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
625 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
626 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
627 #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
628 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
629 #define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
630 #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
631 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
632 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
633 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
634 #define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
635 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
636 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
637 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
638 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
639 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
640 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
641 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
642 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
643 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
644 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
645 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
646 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
647 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
648 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
649 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
650 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
651 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
652 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
653 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
654 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
662 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
663 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
664 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
665 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
669 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
670 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
671 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
672 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
673 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
674 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
683 #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
686 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
687 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
688 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
689 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
690 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
691 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
692 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
693 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
695 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
696 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
697 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
698 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
699 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
700 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
701 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
702 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
703 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
704 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
705 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
706 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
707 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
708 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
709 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
710 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
711 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
712 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
713 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
714 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
715 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
716 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
717 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
718 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
719 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
720 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
721 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
722 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
723 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
724 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
729 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
733 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
739 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
741 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
742 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
743 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
744 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
747 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
753 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
755 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
756 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
757 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
758 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
759 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
760 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
761 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
762 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
763 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
764 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
765 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
766 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
767 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
768 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
769 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
770 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
771 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
772 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
773 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
774 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
775 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
776 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
777 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
778 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
779 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
780 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
781 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
782 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
783 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
784 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
785 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
786 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
787 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
790 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
795 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
798 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
802 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
809 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
812 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
813 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
815 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
819 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
824 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
829 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
831 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
863 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
911 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
972 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
986 #define SYS_RGSR_EL1_SEED_SHIFT 8
998 #define TRFCR_ELx_TS_SHIFT 5
1013 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1197 * set mask are set. Other bits are left as-is.