Lines Matching +full:1 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
97 #define PSTATE_SSBS pstate_field(3, 1)
112 /* Register-based PAN access, for save/restore purposes */
118 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
120 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
121 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
122 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
123 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
124 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
125 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
126 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
130 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
131 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
132 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
134 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
135 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
136 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
138 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
139 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
140 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
142 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
144 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
145 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
146 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
148 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
149 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
150 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
152 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
153 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
154 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
167 #include "asm/sysreg-defs.h"
180 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
181 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
183 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
187 #define OSLSR_EL1_OSLK BIT(1)
189 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
190 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
191 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
193 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
194 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
198 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
200 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
201 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
202 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
203 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
204 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
205 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
206 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
208 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
209 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
210 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
212 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
213 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
216 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
217 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
218 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
219 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
220 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
228 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
230 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
235 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
236 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
237 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
245 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
246 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
248 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
249 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
250 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
251 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
252 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
253 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
254 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
255 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
260 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
261 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
262 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
263 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
264 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
265 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
266 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
267 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
268 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
269 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
270 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
271 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
274 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
282 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
283 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
284 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
286 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
290 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
291 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
292 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
293 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
296 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
301 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
304 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
308 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
309 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
313 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
315 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
322 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
326 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
328 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
331 /* When PAR_EL1.F == 1 */
332 #define SYS_PAR_EL1_FST GENMASK(6, 1)
340 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
343 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
349 #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
374 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
383 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
386 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
391 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
396 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
399 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
403 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
405 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
411 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
415 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
417 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
420 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
423 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
428 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
430 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
439 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
444 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
450 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
457 * n: 0-15
459 * Group 1 of activity monitors (auxiliary):
463 * n: 0-15
466 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
467 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
468 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
469 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
473 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
479 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
484 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
487 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
491 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
502 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
507 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
508 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
509 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
510 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
511 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
512 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
513 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
514 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
517 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
519 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
520 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
522 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
524 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
526 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
527 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
529 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
532 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
533 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
534 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
546 #define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1)
550 #define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1)
556 #define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7)
559 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
561 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
564 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
570 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
577 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
581 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
585 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
591 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
595 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
601 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
603 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
605 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
615 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
617 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
620 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
623 /* VHE encodings for architectural EL0/1 system registers */
625 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
626 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
627 #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
628 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
629 #define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
630 #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
632 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
636 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
637 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
638 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
646 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
647 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
648 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
650 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
653 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
656 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
659 #define AT_Op0 1
660 #define AT_CRn 7
663 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
667 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
670 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
674 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
678 #define TLBI_Op0 1
686 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
687 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
688 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
689 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
690 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
691 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
692 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
693 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
695 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
696 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
697 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
698 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
699 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
700 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
701 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
702 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
703 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
704 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
705 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
706 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
707 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
708 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
709 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
710 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
711 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
712 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
713 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
714 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
715 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
716 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
717 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
718 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
719 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
720 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
721 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
722 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
723 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
724 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
725 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
726 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
727 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
728 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
729 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
730 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
731 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
732 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
733 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
734 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
735 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
736 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
737 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
738 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
739 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
740 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
741 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
742 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
743 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
744 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
745 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
746 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
747 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
748 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
749 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
750 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
751 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
752 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
753 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
754 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
755 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
756 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
757 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
758 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
759 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
760 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
761 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
762 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
763 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
764 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
765 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
766 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
767 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
768 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
769 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
770 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
771 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
772 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
773 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
774 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
775 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
776 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
777 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
778 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
779 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
780 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
781 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
782 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
783 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
784 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
785 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
786 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
787 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
788 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
789 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
790 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
791 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
792 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
793 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
794 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
795 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
796 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
797 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
798 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
799 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
800 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
801 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
802 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
803 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
804 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
805 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
806 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
807 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
808 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
809 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
810 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
811 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
812 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
813 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
814 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
815 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
816 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
817 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
818 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
819 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
820 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
823 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
824 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
825 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
826 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
828 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
829 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
830 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
831 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
832 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
833 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
859 #define SCTLR_ELx_A (BIT(1))
972 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
991 #define SYS_TFSR_EL1_TF1_SHIFT 1
992 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
993 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
1004 #define TRFCR_ELx_ExTRE BIT(1)
1009 #define ICH_MISR_EOI (1 << 0)
1010 #define ICH_MISR_U (1 << 1)
1013 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1015 #define ICH_LR_EOI (1ULL << 41)
1016 #define ICH_LR_GROUP (1ULL << 60)
1017 #define ICH_LR_HW (1ULL << 61)
1019 #define ICH_LR_PENDING_BIT (1ULL << 62)
1020 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
1027 #define ICH_HCR_EN (1 << 0)
1028 #define ICH_HCR_UIE (1 << 1)
1029 #define ICH_HCR_NPIE (1 << 3)
1030 #define ICH_HCR_TC (1 << 10)
1031 #define ICH_HCR_TALL0 (1 << 11)
1032 #define ICH_HCR_TALL1 (1 << 12)
1033 #define ICH_HCR_TDIR (1 << 14)
1039 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
1041 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
1043 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
1045 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
1047 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1049 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1053 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
1054 #define ICH_VMCR_ENG1_SHIFT 1
1055 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
1059 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
1061 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1063 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
1065 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
1067 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
1197 * set mask are set. Other bits are left as-is.