Lines Matching +full:1 +full:v0
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
41 pmull r0.1q, m0.1d, m1.1d; \
42 pmull T1.1q, m0.1d, T0.1d; \
43 pmull2 T0.1q, m0.2d, T0.2d; \
44 pmull2 r1.1q, m0.2d, m1.2d; \
59 pmull r0.1q, m0.1d, m1.1d; \
60 pmull r2.1q, m2.1d, m3.1d; \
61 pmull r4.1q, m4.1d, m5.1d; \
62 pmull r6.1q, m6.1d, m7.1d; \
63 pmull T1.1q, m0.1d, T0.1d; \
64 pmull T3.1q, m2.1d, T2.1d; \
65 pmull T5.1q, m4.1d, T4.1d; \
66 pmull T7.1q, m6.1d, T6.1d; \
67 pmull2 T0.1q, m0.2d, T0.2d; \
68 pmull2 T2.1q, m2.2d, T2.2d; \
69 pmull2 T4.1q, m4.2d, T4.2d; \
70 pmull2 T6.1q, m6.2d, T6.2d; \
71 pmull2 r1.1q, m0.2d, m1.2d; \
72 pmull2 r3.1q, m2.2d, m3.2d; \
73 pmull2 r5.1q, m4.2d, m5.2d; \
74 pmull2 r7.1q, m6.2d, m7.2d; \
101 pmull2 T0.1q, r1.2d, rconst.2d; \
106 pmull T0.1q, r1.1d, rconst.1d; \
113 pmull r0.1q, m0.1d, m1.1d; \
115 pmull T1.1q, m0.1d, T0.1d; \
117 pmull2 T0.1q, m0.2d, T0.2d; \
119 pmull2 r1.1q, m0.2d, m1.2d; \
146 pmull r0.1q, m0.1d, m1.1d; \
147 pmull r2.1q, m2.1d, m3.1d; \
148 pmull r4.1q, m4.1d, m5.1d; \
152 pmull T1.1q, m0.1d, T0.1d; \
153 pmull T3.1q, m2.1d, T2.1d; \
154 pmull T5.1q, m4.1d, T4.1d; \
158 pmull2 T0.1q, m0.2d, T0.2d; \
159 pmull2 T2.1q, m2.2d, T2.2d; \
160 pmull2 T4.1q, m4.2d, T4.2d; \
164 pmull2 r1.1q, m0.2d, m1.2d; \
165 pmull2 r3.1q, m2.2d, m3.2d; \
166 pmull2 r5.1q, m4.2d, m5.2d; \
209 mov vctr.d[1], x9; \
210 add w6, w9, #1; \
218 /* the lower 32-bits of initial IV is always be32(1) */ \
222 mov vctr0.d[1], x9; \
236 /* can be the same as input v0-v3 */
237 #define RR1 v0
275 rev32 v0.16b, RZERO.16b
276 SM4_CRYPT_BLK_BE(v0)
278 /* H ^ 1 */
279 rbit RH1.16b, v0.16b
322 ld1 {v0.16b-v3.16b}, [x2], #64
324 rbit v0.16b, v0.16b
333 * (in3) * H^1 => rr6:rr7
335 eor RHASH.16b, RHASH.16b, v0.16b
355 sub w3, w3, #1
357 ld1 {v0.16b}, [x2], #16
358 rbit v0.16b, v0.16b
359 eor RHASH.16b, RHASH.16b, v0.16b
410 inc32_le128(v0) /* +0 */
411 inc32_le128(v1) /* +1 */
417 SM4_CRYPT_BLK4(v0, v1, v2, v3)
419 eor v0.16b, v0.16b, RTMP0.16b
423 st1 {v0.16b-v3.16b}, [x1], #64
427 rbit v0.16b, v0.16b
436 * (in3) * H^1 => rr6:rr7
438 eor RHASH.16b, RHASH.16b, v0.16b
464 inc32_le128(v0)
468 SM4_CRYPT_BLK(v0)
470 eor v0.16b, v0.16b, RTMP0.16b
471 st1 {v0.16b}, [x1], #16
474 rbit v0.16b, v0.16b
475 eor RHASH.16b, RHASH.16b, v0.16b
484 inc32_le128(v0)
485 SM4_CRYPT_BLK(v0)
495 ldrb w0, [x2], #1 /* get 1 byte from input */
496 umov w6, v0.b[0] /* get top crypted byte */
498 strb w6, [x1], #1 /* store out byte */
501 ext v0.16b, v0.16b, v0.16b, #1
503 ins v0.b[15], w6
505 subs w4, w4, #1
509 tbl v0.16b, {v0.16b}, v3.16b
512 rbit v0.16b, v0.16b
513 eor RHASH.16b, RHASH.16b, v0.16b
563 /* v0-v2 for building CTRs, v3-v5 for saving inputs */
623 inc32_le128(v0) /* +0 */
625 inc32_le128(v1) /* +1 */
633 SM4_CRYPT_PMUL_128x128_BLK3(v0, v1, v2,
638 eor v0.16b, v0.16b, v3.16b
644 st1 {v0.16b-v2.16b}, [x1], #(3 * 16)
658 inc32_le128(v0)
663 SM4_CRYPT_PMUL_128x128_BLK(v0, RR0, RR1, RHASH, RH1, RTMP0, RTMP1)
665 eor v0.16b, v0.16b, v3.16b
669 st1 {v0.16b}, [x1], #16
676 inc32_le128(v0)
677 SM4_CRYPT_BLK(v0)
687 ldrb w0, [x2], #1 /* get 1 byte from input */
688 umov w6, v0.b[0] /* get top crypted byte */
690 strb w6, [x1], #1 /* store out byte */
693 ext v0.16b, v0.16b, v0.16b, #1
695 ins v0.b[15], w0
697 subs w4, w4, #1
701 tbl v0.16b, {v0.16b}, v3.16b
704 rbit v0.16b, v0.16b
705 eor RHASH.16b, RHASH.16b, v0.16b