Lines Matching +full:3 +full:v3
32 * registers v0-v3. It performs matrix operations on four words in parallel,
47 eor v3.16b, v3.16b, v0.16b
48 rev32 v3.8h, v3.8h
51 add v2.4s, v2.4s, v3.4s
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
62 add v2.4s, v2.4s, v3.4s
67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
72 ext v3.16b, v3.16b, v3.16b, #12
76 eor v3.16b, v3.16b, v0.16b
77 rev32 v3.8h, v3.8h
80 add v2.4s, v2.4s, v3.4s
87 eor v3.16b, v3.16b, v0.16b
88 tbl v3.16b, {v3.16b}, v12.16b
91 add v2.4s, v2.4s, v3.4s
96 // x1 = shuffle32(x1, MASK(2, 1, 0, 3))
98 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
100 // x3 = shuffle32(x3, MASK(0, 3, 2, 1))
101 ext v3.16b, v3.16b, v3.16b, #4
118 // x0..3 = s0..3
119 ld1 {v0.4s-v3.4s}, [x0]
139 add v3.4s, v3.4s, v11.4s
140 eor v3.16b, v3.16b, v7.16b
142 st1 {v0.16b-v3.16b}, [x1]
156 ld1 {v0.4s-v3.4s}, [x0]
162 st1 {v3.4s}, [x1]
213 // x0..15[0-3] = s0..3[0..3]
215 ld4r { v0.4s- v3.4s}, [x0]
223 mov a3, v3.s[0]
251 add v3.4s, v3.4s, v7.4s
260 eor v15.16b, v15.16b, v3.16b
318 add v3.4s, v3.4s, v7.4s
327 eor v15.16b, v15.16b, v3.16b
385 add v3.4s, v3.4s, v4.4s
394 eor v14.16b, v14.16b, v3.16b
452 add v3.4s, v3.4s, v4.4s
461 eor v14.16b, v14.16b, v3.16b
515 // x12 += counter values 0-3
518 // x0[0-3] += s0[0]
519 // x1[0-3] += s0[1]
520 // x2[0-3] += s0[2]
521 // x3[0-3] += s0[3]
531 add v3.4s, v3.4s, v19.4s
542 // x4[0-3] += s1[0]
543 // x5[0-3] += s1[1]
544 // x6[0-3] += s1[2]
545 // x7[0-3] += s1[3]
563 // x8[0-3] += s2[0]
564 // x9[0-3] += s2[1]
565 // x10[0-3] += s2[2]
566 // x11[0-3] += s2[3]
584 // x12[0-3] += s3[0]
585 // x13[0-3] += s3[1]
586 // x14[0-3] += s3[2]
587 // x15[0-3] += s3[3]
612 zip1 v18.4s, v2.4s, v3.4s
614 zip2 v19.4s, v2.4s, v3.4s
687 zip1 v3.2d, v28.2d, v30.2d
701 eor v19.16b, v19.16b, v3.16b
753 tbl v28.16b, {v0.16b-v3.16b}, v28.16b
754 tbl v29.16b, {v0.16b-v3.16b}, v29.16b
755 tbl v30.16b, {v0.16b-v3.16b}, v30.16b
756 tbl v31.16b, {v0.16b-v3.16b}, v31.16b
767 tbl v3.16b, {v8.16b-v11.16b}, v7.16b
772 eor v31.16b, v31.16b, v3.16b
778 .Lt320: cbz x7, 3f // exactly 256 bytes?
784 tbl v3.16b, {v12.16b-v15.16b}, v7.16b
789 eor v31.16b, v31.16b, v3.16b
791 3: st1 {v24.16b-v27.16b}, [x1]
804 CTRINC: .word 1, 2, 3, 4