Lines Matching +full:0 +full:x3ffc

41 	memory@0 {
43 		reg = <0x0 0x0 0x0 0x80000000>;
48 		#clock-cells = <0>;
54 		#clock-cells = <0>;
60 		#clock-cells = <0>;
68 	pinctrl-0 = <&pinctrl_can1_default>;
112 	pinctrl-0 = <&pinctrl_gem3_default>;
115 		#size-cells = <0>;
119 			reg = <0xc>;
120 			ti,rx-internal-delay = <0x8>;
121 			ti,tx-internal-delay = <0xa>;
122 			ti,fifo-depth = <0x1>;
141 	pinctrl-0 = <&pinctrl_i2c1_default>;
150 		#size-cells = <0>;
151 		reg = <0x74>;
152 		i2c@0 {
154 			#size-cells = <0>;
155 			reg = <0>;
159 			 *    0 - 256B address 0x54
160 			 * 256B - 512B address 0x55
161 			 * 512B - 768B address 0x56
162 			 * 768B - 1024B address 0x57
166 				reg = <0x54>;
174 			#size-cells = <0>;
181 			#size-cells = <0>;
185 				reg = <0x43>; /* pmbus / i2c 0x13 */
189 				reg = <0x44>; /* pmbus / i2c 0x14 */
195 			#size-cells = <0>;
199 				reg = <0x20>;
205 				 * 0 - IRPS5401_ALERT_B
219 			#size-cells = <0>;
225 			#size-cells = <0>;
442 	flash@0 {
446 		reg = <0x0>;
460 	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
461 	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
462 	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
463 	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
464 	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
465 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
466 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
467 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
477 	pinctrl-0 = <&pinctrl_sdhci1_default>;
485 	pinctrl-0 = <&pinctrl_uart0_default>;
491 	pinctrl-0 = <&pinctrl_uart1_default>;
498 	pinctrl-0 = <&pinctrl_usb0_default>;
500 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
533 	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
534 	       <&psgtr 0 PHY_TYPE_DP 1 3>;