dts/xilinx/zynqmp-zc1751-xm018-dc4.dts

1 // SPDX-License-Identifier: GPL-2.0+
3  * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5  * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 	model = "ZynqMP zc1751-xm018-dc4";
17 	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
29 		spi0 = &qspi;
34 		stdout-path = "serial0:115200n8";
117 	phy-mode = "rgmii-id";
118 	phy-handle = <&ethernet_phy0>;
120 		#address-cells = <1>;
121 		#size-cells = <0>;
122 		ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
125 		ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
128 		ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
131 		ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
139 	phy-mode = "rgmii-id";
140 	phy-handle = <&ethernet_phy7>;
145 	phy-mode = "rgmii-id";
146 	phy-handle = <&ethernet_phy3>;
151 	phy-mode = "rgmii-id";
152 	phy-handle = <&ethernet_phy8>;
164 	clock-frequency = <400000>;
169 	clock-frequency = <400000>;
173 &qspi {
176 		compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
177 		#address-cells = <1>;
178 		#size-cells = <1>;
180 		spi-tx-bus-width = <4>;
181 		spi-rx-bus-width = <4>; /* also DUAL configuration possible */
182 		spi-max-frequency = <108000000>; /* Based on DC1 spec */