dts/xilinx/zynqmp-clk-ccf.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
3  * Clock specification for Xilinx ZynqMP
5  * (C) Copyright 2017 - 2022, Xilinx, Inc.
6  * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
14 		bootph-all;
15 		compatible = "fixed-clock";
16 		#clock-cells = <0>;
17 		clock-frequency = <33333333>;
21 		bootph-all;
22 		compatible = "fixed-clock";
23 		#clock-cells = <0>;
24 		clock-frequency = <27000000>;
28 		bootph-all;
29 		compatible = "fixed-clock";
30 		#clock-cells = <0>;
31 		clock-frequency = <0>;
35 		bootph-all;
36 		compatible = "fixed-clock";
37 		#clock-cells = <0>;
38 		clock-frequency = <108000000>;
42 		bootph-all;
43 		compatible = "fixed-clock";
44 		#clock-cells = <0>;
45 		clock-frequency = <27000000>;
50 	zynqmp_clk: clock-controller {
51 		bootph-all;
52 		#clock-cells = <1>;
53 		compatible = "xlnx,zynqmp-clk";
56 		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
165 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
172 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
179 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
186 	assigned-clocks = <&zynqmp_clk GEM_TSU>;
205 &qspi {
215 	assigned-clocks = <&zynqmp_clk SDIO0_REF>;
220 	assigned-clocks = <&zynqmp_clk SDIO1_REF>;
249 	assigned-clocks = <&zynqmp_clk UART0_REF>;
254 	assigned-clocks = <&zynqmp_clk UART1_REF>;
259 	assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
268 	assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
289 	assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
296 	assigned-clocks = <&zynqmp_clk DP_STC_REF>,