dts/toshiba/tmpv7708.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5  * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000;	/* cpu-release-addr */
18 	#address-cells = <2>;
19 	#size-cells = <2>;
22 		#address-cells = <1>;
23 		#size-cells = <0>;
25 		cpu-map {
58 			compatible = "arm,cortex-a53";
60 			enable-method = "spin-table";
61 			cpu-release-addr = <0x0 0x81100000>;
66 			compatible = "arm,cortex-a53";
68 			enable-method = "spin-table";
69 			cpu-release-addr = <0x0 0x81100000>;
74 			compatible = "arm,cortex-a53";
76 			enable-method = "spin-table";
77 			cpu-release-addr = <0x0 0x81100000>;
82 			compatible = "arm,cortex-a53";
84 			enable-method = "spin-table";
85 			cpu-release-addr = <0x0 0x81100000>;
90 			compatible = "arm,cortex-a53";
92 			enable-method = "spin-table";
93 			cpu-release-addr = <0x0 0x81100000>;
98 			compatible = "arm,cortex-a53";
100 			enable-method = "spin-table";
101 			cpu-release-addr = <0x0 0x81100000>;
106 			compatible = "arm,cortex-a53";
108 			enable-method = "spin-table";
109 			cpu-release-addr = <0x0 0x81100000>;
114 			compatible = "arm,cortex-a53";
116 			enable-method = "spin-table";
117 			cpu-release-addr = <0x0 0x81100000>;
123 		compatible = "arm,armv8-timer";
124 		interrupt-parent = <&gic>;
133 		compatible = "fixed-clock";
134 		#clock-cells = <0>;
135 		clock-frequency = <100000000>;
136 		clock-output-names = "extclk100mhz";
139 	osc2_clk: osc2-clk {
140 		compatible = "fixed-clock";
141 		clock-frequency = <20000000>;
142 		#clock-cells = <0>;
146 		#address-cells = <2>;
147 		#size-cells = <2>;
148 		compatible = "simple-bus";
149 		interrupt-parent = <&gic>;
152 		gic: interrupt-controller@24001000 {
153 			compatible = "arm,gic-400";
154 			interrupt-controller;
155 			#interrupt-cells = <3>;
164 			compatible = "toshiba,tmpv7708-pinctrl";
169 			compatible = "toshiba,gpio-tmpv7708";
171 			#gpio-cells = <0x2>;
172 			gpio-ranges = <&pmux 0 0 32>;
173 			gpio-controller;
174 			interrupt-controller;
175 			#interrupt-cells = <2>;
176 			interrupt-parent = <&gic>;
179 		pipllct: clock-controller@24220000 {
180 			compatible = "toshiba,tmpv7708-pipllct";
182 			#clock-cells = <1>;
187 			compatible = "toshiba,tmpv7708-pismu", "syscon";
189 			#clock-cells = <1>;
190 			#reset-cells = <1>;
197 			pinctrl-names = "default";
198 			pinctrl-0 = <&uart0_pins>;
200 			clock-names = "uartclk", "apb_pclk";
208 			pinctrl-names = "default";
209 			pinctrl-0 = <&uart1_pins>;
211 			clock-names = "uartclk", "apb_pclk";
219 			pinctrl-names = "default";
220 			pinctrl-0 = <&uart2_pins>;
222 			clock-names = "uartclk", "apb_pclk";
230 			pinctrl-names = "default";
231 			pinctrl-0 = <&uart3_pins>;
233 			clock-names = "uartclk", "apb_pclk";
238 			compatible = "snps,designware-i2c";
241 			pinctrl-names = "default";
242 			pinctrl-0 = <&i2c0_pins>;
243 			clock-frequency = <400000>;
244 			#address-cells = <1>;
245 			#size-cells = <0>;
251 			compatible = "snps,designware-i2c";
254 			pinctrl-names = "default";
255 			pinctrl-0 = <&i2c1_pins>;
256 			clock-frequency = <400000>;
257 			#address-cells = <1>;
258 			#size-cells = <0>;
264 			compatible = "snps,designware-i2c";
267 			pinctrl-names = "default";
268 			pinctrl-0 = <&i2c2_pins>;
269 			clock-frequency = <400000>;
270 			#address-cells = <1>;
271 			#size-cells = <0>;
277 			compatible = "snps,designware-i2c";
280 			pinctrl-names = "default";
281 			pinctrl-0 = <&i2c3_pins>;
282 			clock-frequency = <400000>;
283 			#address-cells = <1>;
284 			#size-cells = <0>;
290 			compatible = "snps,designware-i2c";
293 			pinctrl-names = "default";
294 			pinctrl-0 = <&i2c4_pins>;
295 			clock-frequency = <400000>;
296 			#address-cells = <1>;
297 			#size-cells = <0>;
303 			compatible = "snps,designware-i2c";
306 			pinctrl-names = "default";
307 			pinctrl-0 = <&i2c5_pins>;
308 			clock-frequency = <400000>;
309 			#address-cells = <1>;
310 			#size-cells = <0>;
316 			compatible = "snps,designware-i2c";
319 			pinctrl-names = "default";
320 			pinctrl-0 = <&i2c6_pins>;
321 			clock-frequency = <400000>;
322 			#address-cells = <1>;
323 			#size-cells = <0>;
329 			compatible = "snps,designware-i2c";
332 			pinctrl-names = "default";
333 			pinctrl-0 = <&i2c7_pins>;
334 			clock-frequency = <400000>;
335 			#address-cells = <1>;
336 			#size-cells = <0>;
342 			compatible = "snps,designware-i2c";
345 			pinctrl-names = "default";
346 			pinctrl-0 = <&i2c8_pins>;
347 			clock-frequency = <400000>;
348 			#address-cells = <1>;
349 			#size-cells = <0>;
358 			pinctrl-names = "default";
359 			pinctrl-0 = <&spi0_pins>;
360 			num-cs = <1>;
361 			#address-cells = <1>;
362 			#size-cells = <0>;
364 			clock-names = "sspclk", "apb_pclk";
372 			pinctrl-names = "default";
373 			pinctrl-0 = <&spi1_pins>;
374 			num-cs = <1>;
375 			#address-cells = <1>;
376 			#size-cells = <0>;
378 			clock-names = "sspclk", "apb_pclk";
386 			pinctrl-names = "default";
387 			pinctrl-0 = <&spi2_pins>;
388 			num-cs = <1>;
389 			#address-cells = <1>;
390 			#size-cells = <0>;
392 			clock-names = "sspclk", "apb_pclk";
400 			pinctrl-names = "default";
401 			pinctrl-0 = <&spi3_pins>;
402 			num-cs = <1>;
403 			#address-cells = <1>;
404 			#size-cells = <0>;
406 			clock-names = "sspclk", "apb_pclk";
414 			pinctrl-names = "default";
415 			pinctrl-0 = <&spi4_pins>;
416 			num-cs = <1>;
417 			#address-cells = <1>;
418 			#size-cells = <0>;
420 			clock-names = "sspclk", "apb_pclk";
428 			pinctrl-names = "default";
429 			pinctrl-0 = <&spi5_pins>;
430 			num-cs = <1>;
431 			#address-cells = <1>;
432 			#size-cells = <0>;
434 			clock-names = "sspclk", "apb_pclk";
442 			pinctrl-names = "default";
443 			pinctrl-0 = <&spi6_pins>;
444 			num-cs = <1>;
445 			#address-cells = <1>;
446 			#size-cells = <0>;
448 			clock-names = "sspclk", "apb_pclk";
453 			compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
456 			interrupt-names = "macirq";
461 			clock-names = "stmmaceth", "phy_ref_clk";
466 			compatible = "toshiba,visconti-wdt";
473 			compatible = "toshiba,visconti-pwm";
475 			pinctrl-names = "default";
476 			pinctrl-0 = <&pwm_mux>;
477 			#pwm-cells = <2>;
482 			compatible = "toshiba,visconti-pcie";
488 			reg-names = "dbi", "config", "ulreg", "smu", "mpu";
490 			bus-range = <0x00 0xff>;
491 			num-lanes = <2>;
492 			num-viewport = <8>;
494 			#address-cells = <3>;
495 			#size-cells = <2>;
496 			#interrupt-cells = <1>;
501 			interrupt-names = "msi", "intr";
502 			interrupt-map-mask = <0 0 0 7>;
503 			interrupt-map =
508 			max-link-speed = <2>;
510 			clock-names = "ref", "core", "aux";