dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso

1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
3  * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
4  * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
11  * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
14 /dts-v1/;
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/phy/phy-cadence.h>
19 #include <dt-bindings/phy/phy.h>
21 #include "k3-pinctrl.h"
22 #include "k3-serdes.h"
26 		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
27 		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
28 		ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
29 		ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
30 		ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
39 	phy-handle = <&cpsw9g_phy1>;
40 	phy-mode = "qsgmii";
41 	mac-address = [00 00 00 00 00 00];
43 	phy-names = "mac", "serdes";
48 	phy-handle = <&cpsw9g_phy2>;
49 	phy-mode = "qsgmii";
50 	mac-address = [00 00 00 00 00 00];
52 	phy-names = "mac", "serdes";
57 	phy-handle = <&cpsw9g_phy0>;
58 	phy-mode = "qsgmii";
59 	mac-address = [00 00 00 00 00 00];
61 	phy-names = "mac", "serdes";
66 	phy-handle = <&cpsw9g_phy3>;
67 	phy-mode = "qsgmii";
68 	mac-address = [00 00 00 00 00 00];
70 	phy-names = "mac", "serdes";
75 	pinctrl-names = "default";
76 	pinctrl-0 = <&mdio0_default_pins>;
78 	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
79 	reset-post-delay-us = <120000>;
80 	#address-cells = <1>;
81 	#size-cells = <0>;
84 	cpsw9g_phy0: ethernet-phy@16 {
87 	cpsw9g_phy1: ethernet-phy@17 {
90 	cpsw9g_phy2: ethernet-phy@18 {
93 	cpsw9g_phy3: ethernet-phy@19 {
99 	/* Power-up ENET1 EXPANDER PHY. */
100 	qsgmii-line-hog {
101 		gpio-hog;
103 		output-low;
107 	mux-sel-hog {
108 		gpio-hog;
110 		output-high;
115 	mdio0_default_pins: mdio0-default-pins {
116 		pinctrl-single,pins = <
124 	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
137 	#address-cells = <1>;
138 	#size-cells = <0>;
142 		cdns,num-lanes = <1>;
143 		#phy-cells = <0>;
144 		cdns,phy-type = <PHY_TYPE_QSGMII>;