dts/ti/k3-j722s.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5  * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
13 #include "k3-pinctrl.h"
18 	interrupt-parent = <&gic500>;
19 	#address-cells = <2>;
20 	#size-cells = <2>;
23 		#address-cells = <1>;
24 		#size-cells = <0>;
26 		cpu-map {
29 					cpu = <&cpu0>;
46 		cpu0: cpu@0 {  label
47 			compatible = "arm,cortex-a53";
50 			enable-method = "psci";
51 			i-cache-size = <0x8000>;
52 			i-cache-line-size = <64>;
53 			i-cache-sets = <256>;
54 			d-cache-size = <0x8000>;
55 			d-cache-line-size = <64>;
56 			d-cache-sets = <128>;
57 			next-level-cache = <&l2_0>;
62 			compatible = "arm,cortex-a53";
65 			enable-method = "psci";
66 			i-cache-size = <0x8000>;
67 			i-cache-line-size = <64>;
68 			i-cache-sets = <256>;
69 			d-cache-size = <0x8000>;
70 			d-cache-line-size = <64>;
71 			d-cache-sets = <128>;
72 			next-level-cache = <&l2_0>;
77 			compatible = "arm,cortex-a53";
80 			enable-method = "psci";
81 			i-cache-size = <0x8000>;
82 			i-cache-line-size = <64>;
83 			i-cache-sets = <256>;
84 			d-cache-size = <0x8000>;
85 			d-cache-line-size = <64>;
86 			d-cache-sets = <128>;
87 			next-level-cache = <&l2_0>;
92 			compatible = "arm,cortex-a53";
95 			enable-method = "psci";
96 			i-cache-size = <0x8000>;
97 			i-cache-line-size = <64>;
98 			i-cache-sets = <256>;
99 			d-cache-size = <0x8000>;
100 			d-cache-line-size = <64>;
101 			d-cache-sets = <128>;
102 			next-level-cache = <&l2_0>;
107 	l2_0: l2-cache0 {
109 		cache-unified;
110 		cache-level = <2>;
111 		cache-size = <0x80000>;
112 		cache-line-size = <64>;
113 		cache-sets = <512>;
118 			compatible = "linaro,optee-tz";
123 			compatible = "arm,psci-1.0";
128 	a53_timer0: timer-cl0-cpu0 {
129 		compatible = "arm,armv8-timer";
137 		compatible = "arm,cortex-a53-pmu";
142 		compatible = "simple-bus";
143 		#address-cells = <2>;
144 		#size-cells = <2>;
160 			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
161 			 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
166 			 <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
167 			 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
201 			compatible = "simple-bus";
202 			#address-cells = <2>;
203 			#size-cells = <2>;
209 			bootph-all;
213 			compatible = "simple-bus";
214 			#address-cells = <2>;
215 			#size-cells = <2>;
221 			bootph-all;
225 	#include "k3-am62p-j722s-common-thermal.dtsi"
229 #include "k3-am62p-j722s-common-main.dtsi"
230 #include "k3-am62p-j722s-common-mcu.dtsi"
231 #include "k3-am62p-j722s-common-wakeup.dtsi"
234 #include "k3-j722s-main.dtsi"