Lines Matching +full:rgmii +full:- +full:rxid
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/net/ti-dp83867.h>
16 #include "k3-pinctrl.h"
20 ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
25 main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins {
26 pinctrl-single,pins = <
32 rgmii1_default_pins: rgmii1-default-pins {
33 pinctrl-single,pins = <
51 p15-hog {
52 /* P15 - EXP_MUX2 */
53 gpio-hog;
55 output-high;
56 line-name = "EXP_MUX2";
62 pinctrl-names = "default";
63 pinctrl-0 = <&rgmii1_default_pins>;
68 pinctrl-names = "default";
69 pinctrl-0 = <&main_cpsw_mdio_default_pins>;
70 #address-cells = <1>;
71 #size-cells = <0>;
73 main_cpsw_phy0: ethernet-phy@0 {
75 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
76 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
77 ti,min-output-impedance;
83 phy-mode = "rgmii-rxid";
84 phy-handle = <&main_cpsw_phy0>;