dts/ti/k3-j7200-som-p0.dtsi

17 		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
18 		      <0x00000008 0x80000000 0x00000000 0x80000000>;
27 			reg = <0x00 0x9e800000 0x00 0x01800000>;
28 			alignment = <0x1000>;
34 			reg = <0x00 0xa0000000 0x00 0x100000>;
40 			reg = <0x00 0xa0100000 0x00 0xf00000>;
46 			reg = <0x00 0xa1000000 0x00 0x100000>;
52 			reg = <0x00 0xa1100000 0x00 0xf00000>;
58 			reg = <0x00 0xa2000000 0x00 0x100000>;
64 			reg = <0x00 0xa2100000 0x00 0xf00000>;
70 			reg = <0x00 0xa3000000 0x00 0x100000>;
76 			reg = <0x00 0xa3100000 0x00 0xf00000>;
81 			reg = <0x00 0xa4000000 0x00 0x00800000>;
82 			alignment = <0x1000>;
87 	mux0: mux-controller-0 {
102 		#phy-cells = <0>;
110 			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
111 			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
112 			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
113 			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
114 			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
115 			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
116 			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
117 			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
118 			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
119 			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
120 			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
121 			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
122 			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
128 			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
129 			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
130 			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
131 			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
132 			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
133 			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
134 			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
135 			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
136 			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
137 			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
138 			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
146 			J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
147 			J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
155 			J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */
163 			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
164 			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
170 			J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */
171 			J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */
182 	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
183 	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
184 		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
186 	flash@0,0 {
188 		reg = <0x00 0x00 0x4000000>;
195 			partition@0 {
197 				reg = <0x0 0x100000>;
202 				reg = <0x100000 0x200000>;
207 				reg = <0x300000 0x400000>;
212 				reg = <0x700000 0x40000>;
217 				reg = <0x800000 0x3800000>;
228 		ti,mbox-rx = <0 0 0>;
229 		ti,mbox-tx = <1 0 0>;
233 		ti,mbox-rx = <2 0 0>;
234 		ti,mbox-tx = <3 0 0>;
243 		ti,mbox-rx = <0 0 0>;
244 		ti,mbox-tx = <1 0 0>;
248 		ti,mbox-rx = <2 0 0>;
249 		ti,mbox-tx = <3 0 0>;
266 	ti,cluster-mode = <0>;
296 	pinctrl-0 = <&main_i2c0_pins_default>;
301 		reg = <0x21>;
304 		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
314 	pinctrl-0 = <&wkup_i2c0_pins_default>;
319 		reg = <0x50>;
324 		reg = <0x48>;
327 		pinctrl-0 = <&pmic_irq_pins_default>;
420 		reg = <0x4c>;
471 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
473 	flash@0 {
475 		reg = <0x0>;
490 			partition@0 {
492 				reg = <0x0 0x100000>;
497 				reg = <0x100000 0x200000>;
502 				reg = <0x300000 0x400000>;
507 				reg = <0x700000 0x40000>;
512 				reg = <0x740000 0x40000>;
517 				reg = <0x800000 0x37c0000>;
522 				reg = <0x3fc0000 0x40000>;
530 	pinctrl-0 = <&main_mcan0_pins_default>;