dts/ti/k3-am654-icssg2.dtso

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5  * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-pinctrl.h"
16 		ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
17 		ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
20 	/* Ethernet node on PRU-ICSSG2 */
21 	icssg2_eth: icssg2-eth {
22 		compatible = "ti,am654-icssg-prueth";
23 		pinctrl-names = "default";
24 		pinctrl-0 = <&icssg2_rgmii_pins_default>;
28 		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
29 				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
30 				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
31 				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
32 				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
33 				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
35 		ti,pruss-gp-mux-sel = <2>,      /* MII mode */
42 		ti,mii-g-rt = <&icssg2_mii_g_rt>;
43 		ti,mii-rt = <&icssg2_mii_rt>;
46 		interrupt-parent = <&icssg2_intc>;
48 		interrupt-names = "tx_ts0", "tx_ts1";
61 		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
62 			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
64 		ethernet-ports {
65 			#address-cells = <1>;
66 			#size-cells = <0>;
69 				phy-handle = <&icssg2_phy0>;
70 				phy-mode = "rgmii-id";
71 				ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
73 				local-mac-address = [00 00 00 00 00 00];
77 				phy-handle = <&icssg2_phy1>;
78 				phy-mode = "rgmii-id";
79 				ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
81 				local-mac-address = [00 00 00 00 00 00];
89 	icssg2_mdio_pins_default: icssg2-mdio-default-pins {
90 		pinctrl-single,pins = <
96 	icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
97 		pinctrl-single,pins = <
129 	pinctrl-names = "default";
130 	pinctrl-0 = <&icssg2_mdio_pins_default>;
131 	#address-cells = <1>;
132 	#size-cells = <0>;
134 	icssg2_phy0: ethernet-phy@0 {
136 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
137 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
140 	icssg2_phy1: ethernet-phy@3 {
142 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
143 		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;