dts/ti/k3-am642.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-am64.dtsi"
14 		#address-cells = <1>;
15 		#size-cells = <0>;
17 		cpu-map {
30 			compatible = "arm,cortex-a53";
33 			enable-method = "psci";
34 			i-cache-size = <0x8000>;
35 			i-cache-line-size = <64>;
36 			i-cache-sets = <256>;
37 			d-cache-size = <0x8000>;
38 			d-cache-line-size = <64>;
39 			d-cache-sets = <128>;
40 			next-level-cache = <&L2_0>;
44 			compatible = "arm,cortex-a53";
47 			enable-method = "psci";
48 			i-cache-size = <0x8000>;
49 			i-cache-line-size = <64>;
50 			i-cache-sets = <256>;
51 			d-cache-size = <0x8000>;
52 			d-cache-line-size = <64>;
53 			d-cache-sets = <128>;
54 			next-level-cache = <&L2_0>;
58 	L2_0: l2-cache0 {
59 		compatible = "cache";
60 		cache-level = <2>;
61 		cache-unified;
62 		cache-size = <0x40000>;
63 		cache-line-size = <64>;
64 		cache-sets = <256>;