dts/ti/k3-am62p5.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include "k3-am62p.dtsi"
15 		#address-cells = <1>;
16 		#size-cells = <0>;
18 		cpu-map {
39 			compatible = "arm,cortex-a53";
42 			enable-method = "psci";
43 			i-cache-size = <0x8000>;
44 			i-cache-line-size = <64>;
45 			i-cache-sets = <256>;
46 			d-cache-size = <0x8000>;
47 			d-cache-line-size = <64>;
48 			d-cache-sets = <128>;
49 			next-level-cache = <&l2_0>;
54 			compatible = "arm,cortex-a53";
57 			enable-method = "psci";
58 			i-cache-size = <0x8000>;
59 			i-cache-line-size = <64>;
60 			i-cache-sets = <256>;
61 			d-cache-size = <0x8000>;
62 			d-cache-line-size = <64>;
63 			d-cache-sets = <128>;
64 			next-level-cache = <&l2_0>;
69 			compatible = "arm,cortex-a53";
72 			enable-method = "psci";
73 			i-cache-size = <0x8000>;
74 			i-cache-line-size = <64>;
75 			i-cache-sets = <256>;
76 			d-cache-size = <0x8000>;
77 			d-cache-line-size = <64>;
78 			d-cache-sets = <128>;
79 			next-level-cache = <&l2_0>;
84 			compatible = "arm,cortex-a53";
87 			enable-method = "psci";
88 			i-cache-size = <0x8000>;
89 			i-cache-line-size = <64>;
90 			i-cache-sets = <256>;
91 			d-cache-size = <0x8000>;
92 			d-cache-line-size = <64>;
93 			d-cache-sets = <128>;
94 			next-level-cache = <&l2_0>;
99 	l2_0: l2-cache0 {
100 		compatible = "cache";
101 		cache-unified;
102 		cache-level = <2>;
103 		cache-size = <0x80000>;
104 		cache-line-size = <64>;
105 		cache-sets = <512>;