dts/ti/k3-am625.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 		#address-cells = <1>;
17 		#size-cells = <0>;
19 		cpu-map {
40 			compatible = "arm,cortex-a53";
43 			enable-method = "psci";
44 			i-cache-size = <0x8000>;
45 			i-cache-line-size = <64>;
46 			i-cache-sets = <256>;
47 			d-cache-size = <0x8000>;
48 			d-cache-line-size = <64>;
49 			d-cache-sets = <128>;
50 			next-level-cache = <&L2_0>;
51 			operating-points-v2 = <&a53_opp_table>;
53 			#cooling-cells = <2>;
57 			compatible = "arm,cortex-a53";
60 			enable-method = "psci";
61 			i-cache-size = <0x8000>;
62 			i-cache-line-size = <64>;
63 			i-cache-sets = <256>;
64 			d-cache-size = <0x8000>;
65 			d-cache-line-size = <64>;
66 			d-cache-sets = <128>;
67 			next-level-cache = <&L2_0>;
68 			operating-points-v2 = <&a53_opp_table>;
70 			#cooling-cells = <2>;
74 			compatible = "arm,cortex-a53";
77 			enable-method = "psci";
78 			i-cache-size = <0x8000>;
79 			i-cache-line-size = <64>;
80 			i-cache-sets = <256>;
81 			d-cache-size = <0x8000>;
82 			d-cache-line-size = <64>;
83 			d-cache-sets = <128>;
84 			next-level-cache = <&L2_0>;
85 			operating-points-v2 = <&a53_opp_table>;
87 			#cooling-cells = <2>;
91 			compatible = "arm,cortex-a53";
94 			enable-method = "psci";
95 			i-cache-size = <0x8000>;
96 			i-cache-line-size = <64>;
97 			i-cache-sets = <256>;
98 			d-cache-size = <0x8000>;
99 			d-cache-line-size = <64>;
100 			d-cache-sets = <128>;
101 			next-level-cache = <&L2_0>;
102 			operating-points-v2 = <&a53_opp_table>;
104 			#cooling-cells = <2>;
108 	a53_opp_table: opp-table {
109 		compatible = "operating-points-v2-ti-cpu";
110 		opp-shared;
113 		opp-200000000 {
114 			opp-hz = /bits/ 64 <200000000>;
115 			opp-supported-hw = <0x01 0x0007>;
116 			clock-latency-ns = <6000000>;
119 		opp-400000000 {
120 			opp-hz = /bits/ 64 <400000000>;
121 			opp-supported-hw = <0x01 0x0007>;
122 			clock-latency-ns = <6000000>;
125 		opp-600000000 {
126 			opp-hz = /bits/ 64 <600000000>;
127 			opp-supported-hw = <0x01 0x0007>;
128 			clock-latency-ns = <6000000>;
131 		opp-800000000 {
132 			opp-hz = /bits/ 64 <800000000>;
133 			opp-supported-hw = <0x01 0x0007>;
134 			clock-latency-ns = <6000000>;
137 		opp-1000000000 {
138 			opp-hz = /bits/ 64 <1000000000>;
139 			opp-supported-hw = <0x01 0x0006>;
140 			clock-latency-ns = <6000000>;
143 		opp-1250000000 {
144 			opp-hz = /bits/ 64 <1250000000>;
145 			opp-supported-hw = <0x01 0x0004>;
146 			clock-latency-ns = <6000000>;
147 			opp-suspend;
151 	L2_0: l2-cache0 {
153 		cache-unified;
154 		cache-level = <2>;
155 		cache-size = <0x80000>;
156 		cache-line-size = <64>;
157 		cache-sets = <512>;