Lines Matching +full:0 +full:x100a0000
39 #size-cells = <0>;
88 /* Cluster 0 */
89 cpucl0_0: cpu@0 {
92 reg = <0x0 0x000>;
96 i-cache-size = <0xc000>;
99 d-cache-size = <0x8000>;
108 reg = <0x0 0x001>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
124 reg = <0x0 0x002>;
128 i-cache-size = <0xc000>;
131 d-cache-size = <0x8000>;
140 reg = <0x0 0x003>;
143 i-cache-size = <0xc000>;
146 d-cache-size = <0x8000>;
156 reg = <0x0 0x100>;
160 i-cache-size = <0xc000>;
163 d-cache-size = <0x8000>;
172 reg = <0x0 0x101>;
176 i-cache-size = <0xc000>;
179 d-cache-size = <0x8000>;
188 reg = <0x0 0x102>;
192 i-cache-size = <0xc000>;
195 d-cache-size = <0x8000>;
204 reg = <0x0 0x103>;
208 i-cache-size = <0xc000>;
211 d-cache-size = <0x8000>;
221 reg = <0x0 0x200>;
225 i-cache-size = <0xc000>;
228 d-cache-size = <0x8000>;
237 reg = <0x0 0x201>;
241 i-cache-size = <0xc000>;
244 d-cache-size = <0x8000>;
253 reg = <0x0 0x202>;
257 i-cache-size = <0xc000>;
260 d-cache-size = <0x8000>;
269 reg = <0x0 0x203>;
273 i-cache-size = <0xc000>;
276 d-cache-size = <0x8000>;
286 cache-size = <0x400000>;
298 arm,psci-suspend-param = <0x0010000>;
342 #clock-cells = <0>;
353 reg = <0 0x84000000 0 0x8000000>;
357 soc: soc@0 {
361 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
362 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
368 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
369 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
375 reg = <0x0 0x10200000 0x0 0x10000>;
386 /* Per context non-secure context interrupts, 0-3 interrupts */
395 reg = <0x0 0x12100000 0x0 0x10000>;
410 /* Per context non-secure context interrupts, 0-7 interrupts */
423 reg = <0x0 0x14900000 0x0 0x10000>;
432 /* Per context non-secure context interrupts, 0-1 interrupts */
439 reg = <0x0 0x15450000 0x0 0x10000>;
448 /* Per context non-secure context interrupts, 0-1 interrupts */
455 reg = <0x0 0x10010000 0x0 0x3000>;
469 reg = <0x0 0x11c10000 0x0 0x3000>;
477 reg = <0x0 0x12610000 0x0 0x3000>;
485 reg = <0x0 0x12630000 0x0 0x500>;
490 reg = <0x0 0x12810000 0x0 0x3000>;
498 reg = <0x0 0x14010000 0x0 0x3000>;
516 reg = <0x0 0x14030000 0x0 0x1000>;
521 reg = <0x0 0x15010000 0x0 0x3000>;
535 reg = <0x0 0x15030000 0x0 0x1000>;
540 reg = <0x0 0x16810000 0x0 0x3000>;
552 reg = <0x0 0x16830000 0x0 0x1000>;
557 reg = <0x0 0x10100000 0x0 0x1000>;
562 iommus = <&smmu_imem 0x800 0x0>;
567 reg = <0x0 0x10110000 0x0 0x1000>;
572 iommus = <&smmu_imem 0x801 0x0>;
577 reg = <0x0 0x14280000 0x0 0x1000>;
582 iommus = <&smmu_peric 0x2 0x0>;
587 reg = <0x0 0x14290000 0x0 0x1000>;
592 iommus = <&smmu_peric 0x1 0x0>;
597 reg = <0x0 0x14180000 0x0 0x100>;
599 dmas = <&pdma1 1>, <&pdma1 0>;
610 reg = <0x0 0x14190000 0x0 0x100>;
623 reg = <0x0 0x11400000 0x0 0x5000>;
628 reg = <0x0 0x100a0000 0x0 0x100>;
637 reg = <0x0 0x100b0000 0x0 0x100>;
646 reg = <0x0 0x100c0000 0x0 0x100>;
655 reg = <0x0 0x14100000 0x0 0x100>;
656 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
665 reg = <0x0 0x14110000 0x0 0x100>;
666 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
675 reg = <0x0 0x14200000 0x0 0x1000>;
678 #size-cells = <0>;
680 pinctrl-0 = <&hs_i2c0_bus>;
688 reg = <0x0 0x14210000 0x0 0x1000>;
691 #size-cells = <0>;
693 pinctrl-0 = <&hs_i2c1_bus>;
701 reg = <0x0 0x14220000 0x0 0x1000>;
704 #size-cells = <0>;
706 pinctrl-0 = <&hs_i2c2_bus>;
714 reg = <0x0 0x14230000 0x0 0x1000>;
717 #size-cells = <0>;
719 pinctrl-0 = <&hs_i2c3_bus>;
727 reg = <0x0 0x14240000 0x0 0x1000>;
730 #size-cells = <0>;
732 pinctrl-0 = <&hs_i2c4_bus>;
740 reg = <0x0 0x14250000 0x0 0x1000>;
743 #size-cells = <0>;
745 pinctrl-0 = <&hs_i2c5_bus>;
753 reg = <0x0 0x14260000 0x0 0x1000>;
756 #size-cells = <0>;
758 pinctrl-0 = <&hs_i2c6_bus>;
766 reg = <0x0 0x14270000 0x0 0x1000>;
769 #size-cells = <0>;
771 pinctrl-0 = <&hs_i2c7_bus>;
779 reg = <0x0 0x140e0000 0x0 0x100>;
789 pinctrl-0 = <&i2s0_bus>;
796 reg = <0x0 0x140f0000 0x0 0x100>;
806 pinctrl-0 = <&i2s1_bus>;
813 reg = <0x0 0x114f0000 0x0 0x1000>;
818 reg = <0x0 0x141f0000 0x0 0x1000>;
824 reg = <0x0 0x15020000 0x0 0x1000>;
830 reg = <0x0 0x14088000 0x0 0x0200>,
831 <0x0 0x14080000 0x0 0x8000>;
837 pinctrl-0 = <&m_can0_bus>;
841 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
847 reg = <0x0 0x14098000 0x0 0x0200>,
848 <0x0 0x14090000 0x0 0x8000>;
854 pinctrl-0 = <&m_can1_bus>;
858 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
864 reg = <0x0 0x140a8000 0x0 0x0200>,
865 <0x0 0x140a0000 0x0 0x8000>;
871 pinctrl-0 = <&m_can2_bus>;
875 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
881 reg = <0x0 0x140b8000 0x0 0x0200>,
882 <0x0 0x140b0000 0x0 0x8000>;
888 pinctrl-0 = <&m_can3_bus>;
892 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
898 reg = <0x0 0x14140000 0x0 0x100>;
903 #size-cells = <0>;
907 samsung,spi-src-clk = <0>;
909 pinctrl-0 = <&spi0_bus>;
916 reg = <0x0 0x14150000 0x0 0x100>;
921 #size-cells = <0>;
925 samsung,spi-src-clk = <0>;
927 pinctrl-0 = <&spi1_bus>;
934 reg = <0x0 0x14160000 0x0 0x100>;
939 #size-cells = <0>;
943 samsung,spi-src-clk = <0>;
945 pinctrl-0 = <&spi2_bus>;
952 reg = <0x0 0x10040000 0x0 0x800>;
975 reg = <0x0 0x12880000 0x0 0x10000>;
984 reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
985 <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */
986 <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */
987 <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */
993 freq-table-hz = <0 0>, <0 0>;
995 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
1003 reg = <0x0 0x15124000 0x0 0x800>;
1006 #phy-cells = <0>;